A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 262-263

  Zhou, Dajiang ^a   You, Zongyuan ^b   Zhu, Jiayi ^b   Kong, Ji ^b   Hong, Yu ^b   Chen, Xianmin ^b   He, Xuewen ^b   Xu, Chen ^b   Zhang, Hang ^b   Zhou, Jinjia ^a   Deng, Ning ^b   Liu, Peilin ^b   Goto, Satoshi ^b  

^a WASEDA UNIVERSITY   (Japan)

^b SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; VLSI CIRCUITS;

CACHE ARCHITECTURE; COST EFFICIENCY; MULTI STANDARD; RESOURCE-SHARING ARCHITECTURES; STATE OF THE ART; SUB-SYSTEMS; VIDEO DECODER CHIPS; VIDEO FORMAT;

MOTION PICTURE EXPERTS GROUP STANDARDS;

EID: 70449365306     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Micron Technology, Inc., TN-46-03 - calculating memory system power for DDR, http://www.micron.com/support/, 2001.
2. C.-C. Lin, et al., "A 160k gates/4.5kB SRAM H.264 video decoder for HDTV applications," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 170-182, January 2007.
3. C.-C. Ju, et al., "A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications," in A-SSCC Dig. Tech. Papers, November 2008, pp. 9-12.