A 160kGate 4.5kB SRAM H.264 video decoder for HDTV applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Lin, C C ^a   Guo, J I ^a   Chang, H C ^a   Yang, Y C ^a   Chen, J W ^a   Tsai, M C ^a   Wang, J S ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; HIGH DEFINITION TELEVISION; VIDEO SIGNAL PROCESSING;

ARCHITECTURAL OPTIMIZATION; VIDEO DECODERS;

IMAGE CODING;

EID: 34548826055     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Joint Video Team (JVT) of ISO/IEC MPEG&ITU-T VCEG, "ISO/IEC 14496-10," May, 2003.
2. Y. W. Huang, et al., "A 1.3TOPS H.264/AVC Single-Chip Encoder for HDTV Applications," ISSCC Dig. Tech. Papers, pp. 128-129, Feb., 2005.
3. Y. Hu, A. Simpson, K. McAdoo, and J. Cush, "A High Definition H.264/AVC Hardware Video Decoder Core for Multimedia SoCs," Proc. ISCE 2004, pp. 385-389, Sept., 2004.
4. T. W. Chen, et al., "Architecture Design of H.264/AVC Decoder with Hybrid Task Pipelining for High Definition Videos," Proc. ISCAS, pp. 2931-2934, May, 2005.
5. T. A. Lin, et al., "An H.264/AVC Decoder with 4×4 Block-Level Pipeline," Proc. ISCAS, pp. 1810-1813, May, 2005.
6. H. Y. Kang, et al., "MPEG-4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller," Proc. ISCAS, vol. II, pp. 145-148, May, 2004.