A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 171-172

  Zhou, Dajiang ^a   Zhou, Jinjia ^a   He, Xun ^a   Kong, Ji ^b   Zhu, Jiayi ^b   Liu, Peilin ^b   Goto, Satoshi ^a  

^a WASEDA UNIVERSITY   (Japan)

^b SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; CORE ENERGY; H.264/AVC; LOSSLESS; MAXIMUM THROUGH-PUT; PARALLELIZATIONS; POWER SAVINGS; RECOMPRESSION; VIDEO DECODERS;

DECODING; MOTION PICTURE EXPERTS GROUP STANDARDS;

VLSI CIRCUITS;

EID: 77958004818     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560311     Document Type: Conference Paper

References (3)

1. D. Zhou, et al., "A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective," in Tech. Dig. Symp. VLSI Circuits, pp. 262-263, 2009.
2. C.-C. Lin, et al., "A 160K gates/4.5KB SRAM H.264 video decoder for HDTV applications," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 170-181, 2007.
3. http://www.micron.com/support/part-info/powercalc.