Simulation of the electrostatic and transport properties of 3D-stacked GAA silicon nanowire FETs

Solid-State Electronics

Volumn 59, Issue 1, 2011, Pages 62-67

  Ruiz, F G ^a   Tienda Luna, I M ^a   Godoy, A ^a   Sampedro, C ^a   Gamiz F ^a   Donetti, L ^a  

^a UNIVERSITY OF GRANADA   (Spain)

Author keywords

Electron mobility; Gate all Around (GAA) MOSFETs; Multi channel nanowires; Multiple gate devices; Silicon on Insulator

Indexed keywords

COMPREHENSIVE ANALYSIS; DINGER EQUATION; FABRICATION PROCESS; GATE ELECTROSTATICS; GATE-ALL-AROUND; MOSFETS; MULTI-CHANNEL NANOWIRES; MULTIPLE-GATE DEVICES; SELF-CONSISTENT SOLUTION; SIGE LAYERS; SILICON NANOWIRE FETS; SILICON NANOWIRES; SILICON-ON-INSULATOR; STACKED GATE; TECHNOLOGY NODES; TOTAL CHARGE; TRIGATE; WAFER SURFACE;

ELECTRON MOBILITY; ELECTROSTATICS; GALLIUM ALLOYS; MOSFET DEVICES; NANOWIRES; THREE DIMENSIONAL; TRANSPORT PROPERTIES;

SILICON WAFERS;

EID: 79953051974     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2011.01.005     Document Type: Conference Paper

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