메뉴 건너뛰기




Volumn 58, Issue 3, 2011, Pages 609-616

Comparison of 4T and 6T FinFET SRAM cells for subthreshold operation considering variability-A model-based approach

Author keywords

Fin shaped field effect transistor (FinFET); static noise margin (SNM); subthreshold static random access memory (SRAM); variability

Indexed keywords

4-T CELL; 4T SRAM; 6T-CELL; BIT LINES; CELL STABILITY; DESIGN MARGIN; DEVICE VARIATIONS; IDEAL VALUES; MODEL BASED APPROACH; READ DISTURB; SRAM CELL; STATIC NOISE MARGIN; STATIC NOISE MARGIN (SNM); STATIC RANDOM ACCESS MEMORY; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; SUBTHRESHOLD REGION; VARIABILITY; WRITE OPERATIONS;

EID: 79952038442     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2096225     Document Type: Article
Times cited : (36)

References (19)
  • 2
    • 34548813602 scopus 로고    scopus 로고
    • A high-density subthreshold SRAM with data-independent bitline leakage and virtual-ground replica scheme
    • T.-H. Kim, J. Liu, J. Keane, and C. H. Kim, "A high-density subthreshold SRAM with data-independent bitline leakage and virtual-ground replica scheme," in Proc. ISSCC Tech. Dig., 2007, pp. 330-331.
    • (2007) Proc. ISSCC Tech. Dig. , pp. 330-331
    • Kim, T.-H.1    Liu, J.2    Keane, J.3    Kim, C.H.4
  • 3
    • 49549103577 scopus 로고    scopus 로고
    • A 32 Kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS
    • I. J. Chang, J.-J. Kim, S. P. Park, and K. Roy, "A 32 Kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS," in Proc. ISSCC Tech. Dig., 2008, pp. 388-389.
    • (2008) Proc. ISSCC Tech. Dig. , pp. 388-389
    • Chang, I.J.1    Kim, J.-J.2    Park, S.P.3    Roy, K.4
  • 4
    • 34748830993 scopus 로고    scopus 로고
    • A 160 mV robust schmitt trigger based subthreshold SRAM
    • DOI 10.1109/JSSC.2007.897148
    • J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV robust Schmitt trigger based subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007. (Pubitemid 47483011)
    • (2007) IEEE Journal of Solid-State Circuits , vol.42 , Issue.10 , pp. 2303-2313
    • Kulkarni, J.P.1    Kim, K.2    Roy, K.3
  • 5
    • 51549097605 scopus 로고    scopus 로고
    • Process variation tolerant SRAM array for ultra low voltage applications
    • J. P. Kulkarni, K. Kim, S. P. Park, and K. Roy, "Process variation tolerant SRAM array for ultra low voltage applications," in Proc. Des. Autom. Conf., 2008, pp. 108-113.
    • (2008) Proc. Des. Autom. Conf. , pp. 108-113
    • Kulkarni, J.P.1    Kim, K.2    Park, S.P.3    Roy, K.4
  • 6
    • 77953125526 scopus 로고    scopus 로고
    • Investigation of cell stability and write ability of FinFET subthreshold SRAM using analytical SNM model
    • Jun.
    • M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, P. Su, and C.-T. Chuang, "Investigation of cell stability and write ability of FinFET subthreshold SRAM using analytical SNM model," IEEE Trans. Electron Devices, vol. 57, no. 6, pp. 1375-1381, Jun. 2010.
    • (2010) IEEE Trans. Electron Devices , vol.57 , Issue.6 , pp. 1375-1381
    • Fan, M.-L.1    Wu, Y.-S.2    Hu, V.P.-H.3    Su, P.4    Chuang, C.-T.5
  • 7
    • 4444275443 scopus 로고    scopus 로고
    • Double gate-MOSFET subthreshold circuit for ultralow power applications
    • Sep.
    • J. Kim and K. Roy, "Double gate-MOSFET subthreshold circuit for ultralow power applications," IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1468-1474, Sep. 2004.
    • (2004) IEEE Trans. Electron Devices , vol.51 , Issue.9 , pp. 1468-1474
    • Kim, J.1    Roy, K.2
  • 9
    • 30344447576 scopus 로고    scopus 로고
    • Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15 nm UTB SOI based 6T SRAM operation
    • DOI 10.1016/j.sse.2005.10.048, PII S0038110105003163
    • K. Samsudin, B. Cheng, A. R. Brown, S. Roy, and A. Asenov, "Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15 nm UTB SOI based 6T SRAM operation," Solid State Electron., vol. 52, no. 1, pp. 86-93, Jan. 2006. (Pubitemid 43061381)
    • (2006) Solid-State Electronics , vol.50 , Issue.1 , pp. 86-93
    • Samsudin, K.1    Cheng, B.2    Brown, A.R.3    Roy, S.4    Asenov, A.5
  • 10
    • 77954213943 scopus 로고    scopus 로고
    • VDD scalability of FinFET SRAMs: Robustness of different design options against LER-induced variations
    • Sep.
    • E. Baravelli, L. De Marchi, and N. Speciale, " VDD scalability of FinFET SRAMs: Robustness of different design options against LER-induced variations," Solid State Electron., vol. 54, no. 9, pp. 909-918, Sep. 2010.
    • (2010) Solid State Electron. , vol.54 , Issue.9 , pp. 909-918
    • Baravelli, E.1    De Marchi, L.2    Speciale, N.3
  • 11
    • 77952746075 scopus 로고    scopus 로고
    • Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node
    • Jun.
    • C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, C. Mazure, B. Nikolic, and T.-J. K. Liu, "Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node," IEEE Trans. Electron Devices, vol. 57, no. 6, pp. 1301-1309, Jun. 2010.
    • (2010) IEEE Trans. Electron Devices , vol.57 , Issue.6 , pp. 1301-1309
    • Shin, C.1    Cho, M.H.2    Tsukamoto, Y.3    Nguyen, B.-Y.4    Mazure, C.5    Nikolic, B.6    Liu, T.-J.K.7
  • 13
    • 0042912833 scopus 로고    scopus 로고
    • Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs
    • Sep.
    • A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, Sep. 2003.
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.9 , pp. 1837-1852
    • Asenov, A.1    Brown, A.R.2    Davies, J.H.3    Kaya, S.4    Slavcheva, G.5
  • 14
    • 0042532317 scopus 로고    scopus 로고
    • Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness
    • May
    • A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1254-1260, May 2003.
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.5 , pp. 1254-1260
    • Asenov, A.1    Kaya, S.2    Brown, A.R.3
  • 15
    • 44049087277 scopus 로고    scopus 로고
    • Sensitivity of multigate MOSFETs to process variations - An assessment based on analytical solutions of 3-D Poisson's equation
    • DOI 10.1109/TNANO.2008.917835, 4445656
    • Y.-S. Wu and P. Su, "Sensitivity of multigate MOSFETs to process variations-An assessment based on analytical solutions of 3-D Poisson's equation," IEEE Trans. Nanotechnol., vol. 7, no. 3, pp. 299-304, May 2008. (Pubitemid 351711249)
    • (2008) IEEE Transactions on Nanotechnology , vol.7 , Issue.3 , pp. 299-304
    • Wu, Y.-S.1    Su, P.2
  • 16
    • 56549111411 scopus 로고    scopus 로고
    • Sensitivity of gate-all-around nanowire MOSFETs to process variations-A comparison with multigate MOSFETs
    • Nov.
    • Y.-S. Wu and P. Su, "Sensitivity of gate-all-around nanowire MOSFETs to process variations-A comparison with multigate MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3042-3047, Nov. 2008.
    • (2008) IEEE Trans. Electron Devices , vol.55 , Issue.11 , pp. 3042-3047
    • Wu, Y.-S.1    Su, P.2
  • 17
    • 33947117331 scopus 로고    scopus 로고
    • High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices
    • DOI 10.1109/TED.2006.881052
    • M.-H. Chiang, K. Kim, C.-T. Chuang, and C. Tretz, "High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2370-2377, Sep. 2006. (Pubitemid 46405167)
    • (2006) IEEE Transactions on Electron Devices , vol.53 , Issue.9 , pp. 2370-2377
    • Chiang, M.-H.1    Kim, K.2    Chuang, C.-T.3    Tretz, C.4
  • 18
    • 34548818512 scopus 로고    scopus 로고
    • A comparative study of 6T and 4T SRAM cells in double-gate CMOS with statistical variation
    • 4253315, 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
    • B. Giraud, A. Vladimirescu, and A. Amara, "A comparative study of 6T and 4T SRAM cells in double-gate CMOS with statistical variation," in Proc. Int. Conf. Circuits Syst., 2007, pp. 3022-3025. (Pubitemid 47449185)
    • (2007) Proceedings - IEEE International Symposium on Circuits and Systems , pp. 3022-3025
    • Giraud, B.1    Amara, A.2    Vladimirescu, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.