-
1
-
-
33947278802
-
Scaling of multiplegate fully depleted SOI transistors
-
Sep
-
O. Faynot, G. Barna, R. Ritzenthaler, and P. Gidon, "Scaling of multiplegate fully depleted SOI transistors," in Proc. Int. Conf. Solid State Devices Mater., Sep. 2004, pp. 764-765.
-
(2004)
Proc. Int. Conf. Solid State Devices Mater
, pp. 764-765
-
-
Faynot, O.1
Barna, G.2
Ritzenthaler, R.3
Gidon, P.4
-
2
-
-
41149171855
-
Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering
-
Jun
-
J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, and R. Chau, "Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 50-51.
-
(2006)
VLSI Symp. Tech. Dig
, pp. 50-51
-
-
Kavalieros, J.1
Doyle, B.2
Datta, S.3
Dewey, G.4
Doczy, M.5
Jin, B.6
Lionberger, D.7
Metz, M.8
Rachmady, W.9
Radosavljevic, M.10
Shah, U.11
Zelick, N.12
Chau, R.13
-
3
-
-
38649140309
-
-
M. J. H. van Dal, N. Collaert, G. Doombos, G. Vellianitis, G. Curatola, B. J. Pawlak, R. Duffy, C. Jonville, B. Degroote, E. Altamirano, E. Kunnen, M. Demand, S. Beckx, T. Vandeweyer, C. Delvaux, F. Leys, A. Hikavyy, R. Rooyackers, M. Kaiser, R. G. R.Weemaes, S. Biesemans, M. Jurczak, K. Anil, L. Witters, and R. J. P. Lander, Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography, in VLSI Symp. Tech. Dig., Jun. 2007, p. 7A-3.
-
M. J. H. van Dal, N. Collaert, G. Doombos, G. Vellianitis, G. Curatola, B. J. Pawlak, R. Duffy, C. Jonville, B. Degroote, E. Altamirano, E. Kunnen, M. Demand, S. Beckx, T. Vandeweyer, C. Delvaux, F. Leys, A. Hikavyy, R. Rooyackers, M. Kaiser, R. G. R.Weemaes, S. Biesemans, M. Jurczak, K. Anil, L. Witters, and R. J. P. Lander, "Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography," in VLSI Symp. Tech. Dig., Jun. 2007, p. 7A-3.
-
-
-
-
4
-
-
4544367603
-
5 nm-gate nanowire FinFET
-
Jun
-
F. L. Yang, D. H. Lee, H. Y. Chen, C. Y. Chang, S. D. Liu, C.C. Huang, T. X. Chung, H. W. Chen, C. C. Huang, Y. H. Liu, C. C. Wu, C. C. Chen, S. C. Chen, Y. T. Chen, Y. H. Chen, C. J. Chen, B. W. Chan, P. F. Hsu, J. H. Shieh, H. J. Tao, Y. C. Yeo, Y. Li, J. W. Lee, P. Chen, M. S. Liang, and C. Hu, "5 nm-gate nanowire FinFET," in VLSI Symp. Tech. Dig., Jun. 2004, pp. 196-197.
-
(2004)
VLSI Symp. Tech. Dig
, pp. 196-197
-
-
Yang, F.L.1
Lee, D.H.2
Chen, H.Y.3
Chang, C.Y.4
Liu, S.D.5
Huang, C.C.6
Chung, T.X.7
Chen, H.W.8
Huang, C.C.9
Liu, Y.H.10
Wu, C.C.11
Chen, C.C.12
Chen, S.C.13
Chen, Y.T.14
Chen, Y.H.15
Chen, C.J.16
Chan, B.W.17
Hsu, P.F.18
Shieh, J.H.19
Tao, H.J.20
Yeo, Y.C.21
Li, Y.22
Lee, J.W.23
Chen, P.24
Liang, M.S.25
Hu, C.26
more..
-
5
-
-
33847734326
-
High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability
-
S. D. Suk, S. Y. Lee, S. M. Kim, E. J. Yoon, M. S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D. S. Shin, and K. H. Lee, "High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability," in IEDM Tech. Dig., 2005, pp. 717-720.
-
(2005)
IEDM Tech. Dig
, pp. 717-720
-
-
Suk, S.D.1
Lee, S.Y.2
Kim, S.M.3
Yoon, E.J.4
Kim, M.S.5
Li, M.6
Oh, C.W.7
Yeo, K.H.8
Kim, S.H.9
Shin, D.S.10
Lee, K.H.11
-
6
-
-
33646271349
-
High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices
-
May
-
N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices," IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, May 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.5
, pp. 383-386
-
-
Singh, N.1
Agarwal, A.2
Bera, L.K.3
Liow, T.Y.4
Yang, R.5
Rustagi, S.C.6
Tung, C.H.7
Kumar, R.8
Lo, G.Q.9
Balasubramanian, N.10
Kwong, D.L.11
-
7
-
-
0842331307
-
-
J. Wang, E. Polizzi, and M. Lundstrom, A computational study of ballistic silicon nanowire transistors, in IEDM Tech. Dig., 2003, pp. 29.5.1-29.5.4.
-
J. Wang, E. Polizzi, and M. Lundstrom, "A computational study of ballistic silicon nanowire transistors," in IEDM Tech. Dig., 2003, pp. 29.5.1-29.5.4.
-
-
-
-
8
-
-
34249905456
-
Analog/RF performance of Si nanowire MOSFETs and the impact of process variation
-
Jun
-
R.Wang, J. Zhuge, R. Huang, Y. Tian, H. Xiao, L. Zhang, C. Li, X. Zhang, and Y. Wang, "Analog/RF performance of Si nanowire MOSFETs and the impact of process variation," IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1288-1294, Jun. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.6
, pp. 1288-1294
-
-
Wang, R.1
Zhuge, J.2
Huang, R.3
Tian, Y.4
Xiao, H.5
Zhang, L.6
Li, C.7
Zhang, X.8
Wang, Y.9
-
9
-
-
41749091851
-
Impact of a process variation on nanowire and nanotube device performance
-
Sep
-
B. Paul, S. Fujita, M. Okajima, T. H. Lee, H. S. P. Wong, and Y. Nishi, "Impact of a process variation on nanowire and nanotube device performance," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2369-2376, Sep. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.9
, pp. 2369-2376
-
-
Paul, B.1
Fujita, S.2
Okajima, M.3
Lee, T.H.4
Wong, H.S.P.5
Nishi, Y.6
-
10
-
-
44049087277
-
Sensitivity of multigate MOSFETs to process variations - An assessment based on analytical solutions of 3-D Poisson's equation
-
May
-
Y. S. Wu and P. Su, "Sensitivity of multigate MOSFETs to process variations - An assessment based on analytical solutions of 3-D Poisson's equation," IEEE Trans. Nanotechnol., vol. 7, no. 3, pp. 299-304, May 2008.
-
(2008)
IEEE Trans. Nanotechnol
, vol.7
, Issue.3
, pp. 299-304
-
-
Wu, Y.S.1
Su, P.2
-
13
-
-
4444270647
-
A 2-D analytical solution for SCEs in DG MOSFETs
-
Aug
-
X. Liang and Y. Taur, "A 2-D analytical solution for SCEs in DG MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1385-1391, Aug. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.8
, pp. 1385-1391
-
-
Liang, X.1
Taur, Y.2
-
15
-
-
0036684706
-
FinFET design considerations based on 3-D simulation and analytical modeling
-
Aug
-
G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. C. Kan, "FinFET design considerations based on 3-D simulation and analytical modeling," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1411-1419, Aug. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.8
, pp. 1411-1419
-
-
Pei, G.1
Kedzierski, J.2
Oldiges, P.3
Ieong, M.4
Kan, E.C.5
-
16
-
-
56549083878
-
-
Online, Available
-
International Technology Roadmap for Semiconductors. [Online]. Available: http://www.itrs.net/
-
-
-
-
17
-
-
50249139566
-
Impact of parameter variations and random dopant fluctuations on short-channel fully-depleted SOI MOSFETs with extremely thin BOX
-
Workshop Abs
-
T. Ohtou, N. Sugii, and T. Hiramoto, "Impact of parameter variations and random dopant fluctuations on short-channel fully-depleted SOI MOSFETs with extremely thin BOX," in Proc. Silicon Nanoelectron. Workshop, 2006, pp. 15-16. Workshop Abs.
-
(2006)
Proc. Silicon Nanoelectron. Workshop
, pp. 15-16
-
-
Ohtou, T.1
Sugii, N.2
Hiramoto, T.3
-
18
-
-
23844491449
-
Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs
-
Aug
-
V. P. Trivedi and J. G. Fossum, "Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs," IEEE Electron Device Lett., vol. 26, no. 8, pp. 579-582, Aug. 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, Issue.8
, pp. 579-582
-
-
Trivedi, V.P.1
Fossum, J.G.2
-
19
-
-
0001114294
-
Electronic structures and phonon-limited electron mobility of double-gate silicon-on-insulator Si inversion layers
-
Mar
-
M. Shoji and S. Horiguchi, "Electronic structures and phonon-limited electron mobility of double-gate silicon-on-insulator Si inversion layers," J. Appl. Phys., vol. 85, no. 5, pp. 2722-2731, Mar. 1999.
-
(1999)
J. Appl. Phys
, vol.85
, Issue.5
, pp. 2722-2731
-
-
Shoji, M.1
Horiguchi, S.2
-
20
-
-
0027886706
-
Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs
-
Dec
-
Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs," IEEE Electron Device Lett., vol. 14, no. 12, pp. 569-571, Dec. 1993.
-
(1993)
IEEE Electron Device Lett
, vol.14
, Issue.12
, pp. 569-571
-
-
Omura, Y.1
Horiguchi, S.2
Tabe, M.3
Kishi, K.4
-
21
-
-
33646071574
-
Quantum-mechanical effects in trigate SOI MOSFETs
-
May
-
J. P. Colinge, J. C. Alderman, W. Xiong, and C. R. Cleavelin, "Quantum-mechanical effects in trigate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1131-1136, May 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.5
, pp. 1131-1136
-
-
Colinge, J.P.1
Alderman, J.C.2
Xiong, W.3
Cleavelin, C.R.4
|