Short-channel performance improvement by raised source/drain extensions with thin spacers in trigate silicon nanowire MOSFETs

IEEE Electron Device Letters

Volumn 32, Issue 3, 2011, Pages 273-275

  Saitoh, Masumi ^a   Nakabayashi, Yukio ^a   Uchida, Ken ^b   Numata, Toshinori ^a  

^a TOSHIBA CORPORATION   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Drain induced barrier lowering (DIBL); nanowire transistor; parasitic capacitance; parasitic resistance; raised source drain (S D); trigate

Indexed keywords

DRAIN-INDUCED BARRIER LOWERING; NANOWIRE TRANSISTOR; PARASITIC CAPACITANCE; PARASITIC RESISTANCE; RAISED SOURCE/DRAIN; TRIGATE;

CAPACITANCE; SEMICONDUCTING SILICON COMPOUNDS; TRANSISTORS;

NANOWIRES;

EID: 79951958788     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2101043     Document Type: Article

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