메뉴 건너뛰기




Volumn 30, Issue 4, 2009, Pages 407-409

Fluctuation analysis of parasitic resistance in FinFETs with scaled fin thickness

Author keywords

Doping; Extension; FinFET; Fluctuation; Parasitic resistance; Source drain (S D)

Indexed keywords

DOPING; EXTENSION; FINFET; FLUCTUATION; PARASITIC RESISTANCE; SOURCE-DRAIN (S/D);

EID: 67349143366     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2014180     Document Type: Article
Times cited : (26)

References (12)
  • 2
    • 6344290643 scopus 로고
    • Calculated threshold-voltage characterization of an XMOS transistor having an additional bottom gate
    • Aug, Sep
    • T. Sekigawa and Y. Hayashi, "Calculated threshold-voltage characterization of an XMOS transistor having an additional bottom gate," Solid State Electron., vol. 27, no. 8/9, pp. 827-828, Aug./ Sep. 1984.
    • (1984) Solid State Electron , vol.27 , Issue.8-9 , pp. 827-828
    • Sekigawa, T.1    Hayashi, Y.2
  • 5
    • 33646510845 scopus 로고    scopus 로고
    • Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions
    • Apr
    • A. Dixit, K. G. Anil, R. Rooyackers, F. Leys, M. Kaiser, N. Collaert, K. De Meyer, M. Jurczak, and S. Biesemans, "Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions," Solid State Electron., vol. 50, no. 4, pp. 587-593, Apr. 2006.
    • (2006) Solid State Electron , vol.50 , Issue.4 , pp. 587-593
    • Dixit, A.1    Anil, K.G.2    Rooyackers, R.3    Leys, F.4    Kaiser, M.5    Collaert, N.6    De Meyer, K.7    Jurczak, M.8    Biesemans, S.9
  • 6
    • 38649140309 scopus 로고    scopus 로고
    • M. J. H. van Dal, N. Collaert, G. Doornbos, G. Vellianitis, G. Curatola, B. J. Pawlak, R. Duffy, C. Jonville, B. Degroote, E. Altamirano, E. Kunnen, M. Demand, S. Beckx, T. Vandeweyer, C. Delvaux, F. Leys, A. Hikavyy, R. Rooyackers, M. Kaiser, R. G. R.Weemaes, S. Biesemans, M. Jurczak, K. Anil, L. Witters, and R. J. P. Lander, Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography, in VLSI Symp. Tech. Dig., 2007, pp. 110-111.
    • M. J. H. van Dal, N. Collaert, G. Doornbos, G. Vellianitis, G. Curatola, B. J. Pawlak, R. Duffy, C. Jonville, B. Degroote, E. Altamirano, E. Kunnen, M. Demand, S. Beckx, T. Vandeweyer, C. Delvaux, F. Leys, A. Hikavyy, R. Rooyackers, M. Kaiser, R. G. R.Weemaes, S. Biesemans, M. Jurczak, K. Anil, L. Witters, and R. J. P. Lander, "Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography," in VLSI Symp. Tech. Dig., 2007, pp. 110-111.
  • 9
    • 0018468995 scopus 로고
    • A new method to determine effective MOSFET channel length
    • May
    • K. Terada and H. Muta, "A new method to determine effective MOSFET channel length," Jpn. J. Appl. Phys., vol. 18, no. 5, pp. 953-959, May 1979.
    • (1979) Jpn. J. Appl. Phys , vol.18 , Issue.5 , pp. 953-959
    • Terada, K.1    Muta, H.2
  • 10
    • 38549148720 scopus 로고    scopus 로고
    • Experimental study on performance improvement in dopant-segregated Schottky metal-oxide-semiconductor field-effect transistors
    • Y. Nishi, A. Kinoshita, D. Hagishima, and J. Koga, "Experimental study on performance improvement in dopant-segregated Schottky metal-oxide-semiconductor field-effect transistors," Jpn. J. Appl. Phys., vol. 47, no. 1, pp. 99-103, 2008.
    • (2008) Jpn. J. Appl. Phys , vol.47 , Issue.1 , pp. 99-103
    • Nishi, Y.1    Kinoshita, A.2    Hagishima, D.3    Koga, J.4
  • 12
    • 58049102621 scopus 로고    scopus 로고
    • R. Duffy, M. J. H. van Dal, B. J. Pawlak, N. Collaert, L. Witters, R. Rooyackers, M. Kaiser, R. G. R. Weemaes, M. Jurczak, and R. J. P. Lander, Improved fin width scaling in fully-depleted FinFETs by source-drain implant optimization, in Proc. 38th ESSDERC, 2008, pp. 334-337.
    • R. Duffy, M. J. H. van Dal, B. J. Pawlak, N. Collaert, L. Witters, R. Rooyackers, M. Kaiser, R. G. R. Weemaes, M. Jurczak, and R. J. P. Lander, "Improved fin width scaling in fully-depleted FinFETs by source-drain implant optimization," in Proc. 38th ESSDERC, 2008, pp. 334-337.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.