Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions

Solid-State Electronics

Volumn 50, Issue 4, 2006, Pages 587-593

  Dixit, A ^a,b   Anil, K G ^a   Rooyackers, R ^a   Leys, F ^a   Kaiser, M ^c   Collaert, N ^a   De Meyer, K ^a,b   Jurczak, M ^a   Biesemans, S ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Fin field effect transistors (FinFETs); Heavily doped S D region (HDD); Multiple gate field effect transistors (MuGFETs); Raised source drain; Selective epitaxial growth (SEG); Series resistance; Silicon on insulator (SOI) MOSFET; Source drain (S D)

Indexed keywords

CMOS INTEGRATED CIRCUITS; DOPING (ADDITIVES); ELECTRIC RESISTANCE; EPITAXIAL GROWTH; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR);

FIN FIELD-EFFECT TRANSISTORS (FINFET); HEAVILY DOPED S/D REGION (HDD); MULTIPLE GATE FIELD-EFFECT TRANSISTORS (MUGFET); RAISED SOURCE/DRAIN; SELECTIVE EPITAXIAL GROWTH (SEG); SERIES RESISTANCES; SOURCE/DRAIN (S/D);

SILICON ON INSULATOR TECHNOLOGY;

EID: 33646510845     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.03.014     Document Type: Article

References (11)

1. Yu B., et al. IEDM Digest (2002) 251-254
2. Xiong W., et al. IEEE Electron Dev Lett 25 8 (2004) 541-543
3. Collaert N., et al. IEEE Electron Dev Lett 25 8 (2004) 568-570
4. Nackaerts A., et al. IEDM Digest (2004) 269-272
5. Antoniadis DA, Symp. In: VLSI tech, 2002. p. 2-5.
6. Anil KG et al. In: Proc ESSDERC, 2003. p. 139-42.
7. Dixit A., et al. IEEE Trans Electron Dev 52 6 (2005) 1132-1140
8. Kedzierski J., et al. IEEE Trans Electron Dev 50 4 (2003) 952-958
9. Dixit A, et al. In: Proc of 6th ULIS conf 2005, April 7-8, 2005. p. 27-30.
10. ISE-TCAD, Release 9.0, User's Manual.
11. Yang F.-L., et al. IEDM Digest (2002) 255-258