Transformable functional nanoscale building blocks with wafer-scale silicon nanowires

Nano Letters

Volumn 11, Issue 2, 2011, Pages 854-859

  Choi, Sung Jin ^a   Ahn, Jae Hyuk ^a   Han, Jin Woo ^a   Seol, Myeong Lok ^a   Moon, Dong Il ^a   Kim, Sungho ^a   Choi, Yang Kyu ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

address decoders; field effect transistor; logic gates; nanoelectromechanical systems; Silicon nanowire

Indexed keywords

ADDRESS DECODERS; FUNCTIONAL DEVICES; MECHANICAL DYNAMICS; MONOLITHICALLY INTEGRATED; NANO ELECTROMECHANICAL SYSTEMS; NANOSCALE BUILDING BLOCKS; NANOSCALE INTEGRATION; SILICON NANOWIRE; SILICON NANOWIRES; TOP-DOWN APPROACH; WAFER-SCALE;

DECODING; ELECTROSTATICS; FIELD EFFECT TRANSISTORS; LOGIC GATES; MESFET DEVICES; MONOLITHIC INTEGRATED CIRCUITS; NANOSTRUCTURED MATERIALS; NANOWIRES; NEMS; SILICON WAFERS;

SEMICONDUCTING SILICON COMPOUNDS;

NANOTUBE; SILICON;

ARTICLE; CHEMISTRY; CRYSTALLIZATION; EQUIPMENT; EQUIPMENT DESIGN; INSTRUMENTATION; METHODOLOGY; NANOTECHNOLOGY; PARTICLE SIZE; SEMICONDUCTOR; ULTRASTRUCTURE;

CRYSTALLIZATION; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; NANOTECHNOLOGY; NANOTUBES; PARTICLE SIZE; SILICON; TRANSISTORS, ELECTRONIC;

EID: 79851485076     PISSN: 15306984     EISSN: 15306992     Source Type: Journal    
DOI: 10.1021/nl104212e     Document Type: Article

References (28)

1. Goldhaber-Gordon, D.; Montemerlo, M. S.; Love, J. C.; Opiteck, G. J.; Ellenbogen, J. C. Proc. IEEE 1997, 85, 521-540
2. Taur, Y.; Buchanan, D. A.; Chen, W.; Frank, D. J.; Ismail, K. E.; Lo, S.-H.; Sai-Halasz, G. A.; Viswanathan, R. G.; Wann, H.-J. C.; Wind, S. J.; Wong, H.-S. Proc. IEEE 1997, 85, 486-504
3. Ellenbogen, J. C.; Love, J. C. Proc. IEEE 2000, 88, 386-426
4. Peercy, P. S. Nature 2000, 406, 1023-1026
5. Wada, Y. Proc. IEEE 2001, 89, 1147-1171
6. Tseng, G. Y.; Ellenbogen, J. C. Science 2001, 294, 1293-1294
7. Hu, J.; Odom, T. W.; Lieber, C. M. Acc. Chem. Res. 1999, 32, 435-445
8. Dekker, C. Phys. Today 1999, 52, 22-28
9. Cui, Y.; Duan, X.; Hu, J.; Lieber, C. M. J. Phys. Chem. B 2000, 104, 5213-5216
10. Duan, X.; Huang, Y.; Cui, Y.; Wang, J.; Lieber, C. M. Nature 2001, 409, 66-69
11. Cui, Y.; Lieber, C. M. Science 2001, 291, 851-853
12. Huang, Y.; Duan, X.; Cui, Y.; Lauhon, L. J.; Kim, K.-H.; Lieber, C. M. Science 2001, 294, 1313-1317
13. Kim, D. R.; Lee, C. H.; Zheng, X. Nano Lett. 2010, 10, 1050-1054
14. Duan, X.; Niu, C.; Sahi, J.; Chen, J.; Parce, J. W.; Empedocles, S.; Goldman, J. L. Nature 2003, 425, 274-278
15. Zhong, Z.; Wang, D.; Cui, Y.; Bockrath, M. W.; Lieber, C. M. Science 2003, 302, 1377-1379
16. Ng, H. T.; Han, J.; Yamada, T.; Nguyen, P.; Chen, Y. P.; Meyyappan, M. Nano Lett. 2004, 4, 1247-1252
17. Javey, A.; Nam, S.; Friedman, R. S.; Yan, H.; Lieber, C. M. Nano Lett. 2007, 7, 773-777
18. Choi, Y. -K.; King, T. -J.; Hu, C. IEEE Electron Device Lett. 2002, 23, 25-27
19. +-doped source/drain (S/D) and p-SiNW as a channel) as a pull-down network on the proposed SiNW-FET, a NOR logic gate can be readily formed, similar to a NAND logic gate.
20. Sze, S. M. Physics of Semiconductor Devices, 3 rd ed.; Willey: New York, 2007; pp 293 - 298.
21. The pn-diodes are generally used for the formation of potential barriers between the S/D and channel in a FET. However, this structure can be changed through the use of a structure without S/D junctions. Whereas previous work using crossed nanowire FETs only utilized highly doped SiNWs without the formation of S/D junctions, in the present study highly doped S/D junctions were formed to employ built-in diodes.
22. Rueckes, T.; Kim, K.; Joselevich, E.; Tseng, G. Y.; Cheung, C.-L.; Lieber, C. M. Science 2000, 289, 94-97
23. OUT does not affect the operation of our logic gates because the low turn-on voltage contributions are reproducible and can be readily accounted for in defining the 0 and 1 states.
24. + poly-Si gates. Therefore, previous pull-up networks in complementary metal oxide semiconductor (CMOS) electronics can be transformed to OR logic gates (Figure 2), and pull-down networks can be transformed to AND logic gates. Also see Supporting Information, Figure S2.
25. DeHon, A. IEEE Trans. Nanotechnol. 2003, 2, 23-32
26. Kong, J.; Franklin, N. R.; Zhou, C.; Chapline, M. G.; Peng, S.; Cho, K.; Dai, H. Science 2000, 287, 622-625
27. Cui, Y.; Wei, Q.; Park, H.; Lieber, C. M. Science 2001, 293, 1289-1292
28. 2 and air. However, after modification, the equivalent thickness of the gate dielectric is close to 6 nm. This difference in the thickness and permittivity of the gate dielectric layer can affect the gate capacitance value and in turn, significantly change the threshold voltage.