A high level power model for Network-on-Chip (NoC) router

Computers and Electrical Engineering

Volumn 35, Issue 6, 2009, Pages 837-845

  Lee, Seung Eun ^a   Bagherzadeh, Nader ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Interconnection network; Multi processor System on Chip (MPSoC); Network on Chip (NoC); Power model

Indexed keywords

CYCLE ACCURATE; GATE-LEVEL ANALYSIS; HIGH-LEVEL POWER ESTIMATION; MACRO MODEL; MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC); NETWORK ON CHIP; NETWORK POWER; NETWORK-ON-CHIP (NOC); POWER MODEL; POWER OPTIMIZATION; POWER PROFILE; POWER-AWARE; SCHEDULING TECHNIQUES; SYSTEM LEVELS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROGRAM COMPILERS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEMS ANALYSIS;

ROUTERS;

EID: 70350573471     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2008.11.023     Document Type: Article

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