A 47 × 10 Gb/s 1.4 mW/Gb/s parallel interface in 45 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 12, 2010, Pages 2828-2837

  O'Mahony, Frank ^a   Jaussi, James E ^a   Kennedy, Joseph ^a   Balamurugan, Ganesh ^a   Mansuri, Mozhgan ^a   Roberts, Clark ^a   Shekhar, Sudip ^a   Mooney, Randy ^a   Casper, Bryan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

I O; interface; link; low area; low power; power management; power states; standby; transceiver

Indexed keywords

I/O; INTERFACE; LINK; LOW AREA; LOW POWER; POWER MANAGEMENTS; POWER STATE; STANDBY;

INTERFACES (COMPUTER); TRANSCEIVERS;

ENERGY MANAGEMENT;

EID: 78650062073     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2076214     Document Type: Conference Paper

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