A low-jitter PLL and repeaterless clock distribution network for a 20Gb/s link

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 29-30

  O'Mahony, Frank ^a   Mansuri, Mozhgan ^a   Casper, Bryan ^a   Jaussi, James E ^a   Mooney, Randy ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Clock distribution; Device noise; I O; Jitter; Link; Parallel; PLL; Power supply noise; VCO

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; JITTER; PHASE LOCKED LOOPS; POWER SUPPLY CIRCUITS;

CLOCK DISTRIBUTION NETWORK; CLOCK GENERATION; DEVICE NOISE; POWER SUPPLY NOISE;

ELECTRIC POWER DISTRIBUTION;

EID: 39749158611     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. G. Balamurugan and N. Shanbhag, "Modeling and mitigation of jitter in high-speed source-synchronous inter-chip communication systems,"ACSSC, pp. 1681-1687, Nov. 2003.
2. B. Casper et. al, "A 20Gb/s forwarded clock transceiver in 90nm CMOS," ISSCC Digest of Tech. Papers, pp. 18-19, Feb. 2006.
3. A Maxim, "A multi-rate 9.953-12.5GHz 0.2mm SiGe BICMOS LC. oscillator with -120dBc/Hz phase noise at 1MHz offset using a variable resistor based varactor," Proc. VLSI, pp. 202-205, June 2005.
4. J. McNeill, "Jitter in ring oscillators," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 870-879, June 1997.