The future of electrical I/O for microprocessors

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Volumn , Issue , 2009, Pages 31-34

  O'Mahony, Frank ^a   Balamurugan, Ganesh ^a   Jaussi, James E ^a   Kennedy, Joseph ^a   Mansuri, Mozhgan ^a   Shekhar, Sudip ^a   Casper, Bryan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Data link; Electrical; I O; Low power; Microprocessor; Scaling; Signaling; Transceiver; Wireline

Indexed keywords

CHANNEL TOPOLOGY; CHIP-TO-CHIP COMMUNICATIONS; DATA LINK; DENSITY SCALING; ELECTRICAL; HIGH LEVEL ARCHITECTURE; HIGH-SPEED; I/O; LEVEL DESIGN; LINK DESIGN; LOW POWER; MULTI-CORE PROCESSOR; POWER EFFICIENCY; STATISTICAL LINKS;

DESIGN; RAILROAD TUNNELS; SIGNALING; TELECOMMUNICATION SYSTEMS; TOPOLOGY; TRANSCEIVERS;

MICROPROCESSOR CHIPS;

EID: 77950654711     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2009.5158087     Document Type: Conference Paper

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