A 4.3 GB/s mobile memory interface with power-efficient bandwidth scaling

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 4, 2010, Pages 889-898

  Leibowitz, Brian ^a   Palmer, Robert ^b   Poulton, John ^b   Frans, Yohan ^a   Li, Simon ^a   Wilson, John ^a   Bucher, Michael ^a   Fuller, Andrew M ^c   Eyles, John ^d   Aleksić, Marko ^a   Greer, Trey ^b   Nguyen, Nhat M ^a  

^a RAMBUS INC   (United States)

^b NVIDIA   (United States)

^c DUKE UNIVERSITY   (United States)

^d NONE

Author keywords

I O; Low power; Memory interface; Power management

Indexed keywords

BIT RATES; CMOS CIRCUITS; CMOS TECHNOLOGY; DATA BANDWIDTH; DIFFERENTIAL SIGNALING; DYNAMIC INTERFACE; DYNAMIC POWER CONSUMPTION; EFFECTIVE BANDWIDTH; EXPLICIT COMMUNICATION; LOW POWER; LOW POWER STATE; LOW STATIC POWER; LOW SWING; LOW-POWER MEMORY; MAXIMUM POWER; MEMORY CONTROLLER; MOBILE MEMORIES; POWER EFFICIENCY; POWER EFFICIENT; POWER MANAGEMENTS; POWER STATE; RAPID TRANSITIONS; SIGNAL INTEGRITY; SYNCHRONOUS COMMUNICATIONS; SYSTEM STATE; VOLTAGE MODE;

ANALOG TO DIGITAL CONVERSION; CLOCKS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER MEASUREMENT; EMBEDDED SYSTEMS; ENERGY MANAGEMENT; SIGNALING;

BANDWIDTH;

EID: 77950212946     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2040230     Document Type: Conference Paper

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