A 72mW 0.03mm2 inductorless 40Gb/s CDR in 65nm SOI CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 226-228

  Toifl, Thomas ^a   Menolfi, Christian ^a   Buchmann, Peter ^a   Hagleitner, Christoph ^a   Kossel, Marcel ^a   Morf, Thomas ^a   Weiss, Jonas ^a   Schmatz, Martin ^a  

^a IBM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; FREQUENCY BANDS; MEASUREMENT THEORY; MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY;

FREQUENCY-OFFSET; SAMPLING PHASES;

CMOS INTEGRATED CIRCUITS;

EID: 34548813071     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373376     Document Type: Conference Paper

References (7)

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3. S. Sidiropoulos, M. Horowitz, "A Semi-Digital Dual Delay-Locked Loop," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov., 1997.
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5. B. Casper, J. Jaussi, F, Oapes Mahony, et al., "A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS, ISSCC Dig. Tech Papers7 pp. 90-91, Feb., 2006.
6. C. Kromer, G. Sialm, C. Menofli, et al., "A 25Cb/s CDR in 90nm CMOS for High-Density Interconnects," ISSCC Dig. Tech Papers, pp. 326-327, Feb., 2006.
7. D. Kucharski, Kornegay, K.T., "2.5 V 43-45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family," IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2154 -2165, Sept., 2006.