Power-centric design of high-speed I/Os

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 867-872

  Hatamkhani, Hamid ^a   Lambrecht, Frank ^b   Stojanovic, Vladimir ^c   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b RAMBUS INC   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Channel model; Convex optimization; I O; Power minimization; Serial link

Indexed keywords

BANDWIDTH; ENERGY DISSIPATION; INPUT OUTPUT PROGRAMS; JITTER; MICROPROCESSOR CHIPS; VOLTAGE CONTROL;

CHANNEL MODEL; CONVEX OPTIMIZATION; POWER MINIMIZATION; SERIAL LINK;

LOGIC DESIGN;

EID: 34547274948     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147130     Document Type: Conference Paper

References (13)

1. International Technology Roadmap Service, http://public.itrs.net
2. J. Hart, et.al., "Implementation of a Fourth-Generation 1.8GHz Dual-Core SPARC V9 Microprocessor", JSSC 01/06, pp210
3. D.C Pham, et.al., "Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor", JSSC 01/06, pp178
4. D. Markovic, et.al., "Methods for True Energy-Performance Optimization", JSSC 08/04 pp1282-93
5. K.L. Wong, et.al., "A sub-30mW 3.6Gbps Transceiver", JSSC, 04/04, pp 602-12
6. J. Kim, M. Horowitz, "Adaptive Supply Serial Links With Sub-1-V Operation and Per-Pin Clock Recovery," JSSC 11/02, pp 1403-13
7. Y. Moon, et.al., "A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control", ISSCC 02/06 pp 84-5
8. B. Casper, et.al., "A 20Gb/s Forward Clock Transceiver in 90nm CMOS", ISSCC 02/06, pp 90-1
9. A. Emami-Neyastak, et al., "A Low-Power Receiver with Switched-Capacitor Summation DFE", VLSI Circuit Symposium 06/06, to appear
10. K.J. Wong, et.al., "A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decisions", VLSI Circuit Symposium 06/06, to appear
11. T. Sakurai, A. R Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas" JSSC 07/92.
12. V. Stojanovic, M. Horowitz, "Modeling and Analysis of High-Speed Links", CICC '03, pp.589-94
13. V. Stojanovic, et.al. "Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication", ICC'04, pp.2799-2806