0.94ps-rms-jitter 0.016mm2 2.5GHz multi-phase generator PLL with 360° digitally programmable phase shift for 10Gb/s serial links

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Toifl, Thomas ^a   Menolfi, Christian ^a   Buchmann, Peter ^a   Kossel, Marcel ^a   Morf, Thomas ^a   Reutemann, Robert ^b   Ruegg, Michael ^b   Schmatz, Martin ^a   Weiss, Jonas ^a  

^a IBM   (Switzerland)

^b Miromico AG   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144455514     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S. Sidiropoulos, M. Horowitz, "A Semi-Digital Dual Delay-Locked Loop," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov., 1997.
2. K. L. Wong et al., "A 27-mW 3.6 Gb/s I/O Transceiver," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 602-612, Apr., 2004.
3. M. Mansuri, C.-K. Ken Yang, "Jitter Optimization Based on Phase-Locked Loop Design Parameters," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1375-1382, Nov., 2002.
4. 2 6T-SRAM Cell," IEDM Tech. Dig., pp. 407-410, 2002.