Power analysis for high-speed I/O transmitters

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 142-145

  Hatamkhani, Hamid ^a   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DATA REDUCTION; DYNAMIC RESPONSE; ELECTRIC LOADS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; OPTIMIZATION; SEMICONDUCTOR MATERIALS; SHRINKFITTING; SIGNAL PROCESSING; TRANSISTORS; TRANSMITTERS;

OUTPUT DATA; RANDOM JITTERS (RJ); TRANSMITTER ARCHITECTURES; TRANSMITTER MODELS;

POWER ELECTRONICS;

EID: 4544368060     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. H. Hatamkhani, et al., "A 10-mw 3.6-Gbps I/0 transmitter", 2003 Symposium on VLSI Circuits, 2003.
2. K. S. Donnelly, et al., "A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC", IEEE Journal of Solid-State Circuits, vol. 31, no. 12, Dec 1996.
3. nd edition, 2003, Pretice Hall.
4. T. Sakurai, A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas" IEEE Journal of Solid-State Circuits, Volume: 27, Issue: 7, Jul 1992.
5. InfiniteBand Architetura Specification.Volume 2. Release 0.97. Intel corporation. Sept 2000.
6. IEEE Std. 1394b - 2002 IEEE Standard for a High-Performance Serial Bus - Amendment 2
7. Semiconductor Ind. Assoc., The International Technology Roadmap for Semiconductors, http://public.itrs.net