A low-noise self-calibrating dynamic comparator for high-speed ADCs

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Volumn , Issue , 2008, Pages 269-272

  Miyahara, Masaya ^a   Asada, Yusuke ^a   Paik, Daehwa ^a   Matsuzawa, Akira ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION TECHNIQUES; CMOS TECHNOLOGY; DYNAMIC COMPARATORS; HIGH-SPEED; INPUT NOISE; LOW NOISE; LOW OFFSET; LOW-POWER CONSUMPTION; OFFSET VOLTAGE; PHASE CLOCKS; QUIESCENT CURRENTS; SELF-CALIBRATING; SIMULATED RESULTS; TWO PHASE;

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CLOCKS; CMOS INTEGRATED CIRCUITS;

COMPARATORS (OPTICAL);

EID: 67649921302     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708780     Document Type: Conference Paper

References (4)

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3. V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas and J. Craninckx "An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in a 90nm Digital CMOS Process," ISSCC Dig. of Tech. Papers, pp.238-239, Feb., 2008.
4. D. Schinkel, E. Mensink, E. Klumperink, Ed Van Tuijl, B. Nauta, "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup-Hold Time," ISSCC Dig. of Tech. Papers, pp.314-315, Feb., 2007.