An 8Gb/s transceiver with 3×-oversampling 2-threshold eye-tracking CDR circuit for -36.8dB-loss backplane

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages

  Fukuda, K ^a   Yamashita, H ^a   Yuki, F ^a   Yagyu, M ^a   Nemoto, R ^a   Takemoto, T ^a   Saito, T ^a   Chujo, N ^a   Yamamoto, K ^a   Kanai, H ^a   Hayashi, A ^a  

^a Hitachi ^*  (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUIT TRACKING; LEARNING SYSTEMS; NETWORKS (CIRCUITS);

BACK PLANES; CDR CIRCUITS; EYE-TRACKING; INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE; OVER-SAMPLING;

TRANSCEIVERS;

EID: 49549108262     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.45230754     Document Type: Conference Paper

References (3)

1. J. F. Bulzacchelli, M. Meghelli, S. V. Rylov, et al., "A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2883-2990, Dec., 2006.
2. J. Ren, H. Lee, Q. Lin, et al., "Precursor ISI Reduction in High-Speed I/O," Symp. VLSI Circuits, pp. 134-135, Jun. 2007.
3. Y. Miki, T. Saito, H. Yamashita, et al, "A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface with Digital Eye-Tracking," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 613-621, Apr. 2004.