A 0.6mW/Gbps, 6.4-8.0Gbps serial link receiver using local injection-locked ring oscillators in 90nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 46-47

  Hu, Kangmin ^a   Jiang, Tao ^a   Wang, Jingguang ^a   O'Mahony, Frank ^b   Chiang, Patrick Yin ^a  

^a Oregon State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Injection locked oscillator; Receiver; Serial link

Indexed keywords

90NM CMOS; BACKPLANES; CLOCK DISTRIBUTION; DATA RATES; GBPS SERIAL LINKS; INJECTION-LOCKED OSCILLATOR; INJECTION-LOCKED RING OSCILLATORS; LINEAR EQUALIZER; LOW POWER; MEASURED RESULTS; POWER EFFICIENCY; QUANTIZERS; RECEIVER; SERIAL LINK; TEST-CHIP;

DEMULTIPLEXING; PHASE LOCKED LOOPS; VLSI CIRCUITS;

OSCILLATORS (ELECTRONIC);

EID: 70449393666     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. M. Tremblay and S. Chaudhry, "A third-generation 65nm 16- core 32-thread plus 32-scout-thread CMT SPARC processor," IEEE ISSCC Dig. Tech. Papers, pp.82-83, Feb. 2008
2. J. Poulton, et al., "A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp.2745-2757, Dec. 2007
3. F. O'Mahony, et al., "A 27Gb/s forwarded-clock I/O receiver using an injection-locked LC-DCO in 45nm CMOS," IEEE ISSCC Dig. Tech. Papers, pp.452-453, Feb. 2008
4. L. Zhang, B. Ciftcioglu, M. Huang, W. Hui, "Injection-locked clocking: a new GHz clock distribution scheme," Proc. IEEE CICC, pp.785-788, Sep. 2006
5. R. Alder, "A study of locking phenomena in oscillators," Proc. IRE, vol.34, pp. 351-356, June 1946, reprinted in Proc. IEEE, vol. 61, pp. 1380-1385, Oct. 1973
6. D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, B. Nauta, "A double-tail latch-type voltage sense amplifier with 18ps setup+hold time," IEEE ISSCC Dig. Tech. Papers, pp. 314-315, Feb. 2007