A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 182-184

  Liu, Yong ^a   Kim, Byungsub ^b   Dickson, Timothy O ^b   Bulzacchelll, John F ^b   Friedman, Daniel J ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349294332     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977368     Document Type: Conference Paper

References (5)

1. J.U. Knickerbocker, C.S. Patel, C.K. Tsang, et al., "3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias," IEEE J. Solid-State Circuits, vol.41, no.8, pp. 1718-1725, Aug., 2006.
2. A. Rylyakov, "An 11Gb/s 2.4mW Half-Rate Sampling 2-Tap DFE Receiver in 65nm CMOS," IEEE Symp. VLSI Circuits, pp. 272-273, June, 2007.
3. E. Mensink, D. Schinkel, E. Klumperink, et al., "A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip Interconnects," ISSCC Dig. Tech. Papers, pp. 414-415, Feb., 2007.
4. P.M. Crespo and M.L. Honig, "Pole-Zero Decision Feedback Equalization with a Rapidly Converging Adaptive IIR Algorithm," IEEE J. Selected Areas in Comm., vol.9, no.6, pp. 817-829, Aug., 1991.
5. T.O. Dickson, J.F. Bulzacchelli, and D.J. Friedman, "A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer with Current-Integrating Summers in 45-nm SOI CMOS Technology," IEEE Symp. VLSI Circuits, pp. 58-59, June, 2008.