Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

Microelectronics Reliability

Volumn 50, Issue 12, 2010, Pages 1907-1914

  Samanta, Piyas ^a,b   Zhu, Chunxiang ^c   Chan, Mansun ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b VIDYASAGAR COLLEGE   (India)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING MEMORIES; CMOS LOGIC; ELECTRICAL STRESS; GATE DIELECTRIC STACKS; GATE VOLTAGES; IN-CONTROL; METAL OXIDE SEMICONDUCTOR; OPERATING VOLTAGE; OXIDE CHARGE; POSITIVE CHARGES; SURFACE STATE;

CHARGE CARRIERS; CHARGE TRAPPING; DEGRADATION; DIELECTRIC MATERIALS; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS;

SILICON COMPOUNDS;

EID: 78649445981     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.07.005     Document Type: Article

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