Control of interface traps in HfO 2 gate dielectric on silicon

Journal of Electronic Materials

Volumn 39, Issue 11, 2010, Pages 2435-2440

  Tan, S Y ^a  

^a CHINESE CULTURE UNIVERSITY   (Taiwan)

Author keywords

HfO 2; High k dielectric; Interface trap; Postdeposition annealing

Indexed keywords

AMORPHOUS INTERFACES; BULK SILICON; CAPACITANCE-VOLTAGE TECHNIQUES; COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES; DEEP TRAP CENTER; DEFECT STATE; ELECTRICAL PERFORMANCE; GATE STACKS; HFO 2; HIGH-K DIELECTRIC; INTERFACE PROPERTY; INTERFACE TRAP DENSITY; INTERFACE TRAPS; INTERFACIAL PROPERTY; POST DEPOSITION ANNEALING; SI SUBSTRATES; SILICON SUBSTRATES; TEM; THERMAL-ANNEALING;

ANNEALING; DEFECT DENSITY; GATE DIELECTRICS; GATES (TRANSISTOR); MOS DEVICES; OXYGEN; SEMICONDUCTOR GROWTH; SILICON; TRANSMISSION ELECTRON MICROSCOPY; X RAY DIFFRACTION; X RAY PHOTOELECTRON SPECTROSCOPY;

HAFNIUM COMPOUNDS;

EID: 78149283819     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-010-1323-0     Document Type: Article

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