A Simulation Study to Evaluate the Feasibility of Midgap Workfunction Metal Gates in 25 nm Bulk CMOS

IEEE Electron Device Letters

Volumn 24, Issue 11, 2003, Pages 707-709

  Maitra, Kingsuk ^a   Misra, Veena ^a  

^a North Carolina State University   (United States)

Author keywords

Bandedge; Bulk; CMOS; DIBL; Metal gates; Midgap; NMOSFETs; PMOSFETs; Simulation; Workfunction

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; MOSFET DEVICES; POLYSILICON;

BANDEDGE; METAL GATES;

GATES (TRANSISTOR);

EID: 0242662109     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.819267     Document Type: Article

References (12)

1. (2001) International Technology Roadmap for Semiconductors. [Online]. Available: www.public.itrs.net
2. I. De, D. Johri, A. Srivastava, and C. M. Osburn, "Impact of gate work-function on device performance at the 50 nm technology node," Solid State Electron., vol. 44, pp. 1077-1080, 2000.
3. Y. Abe, T. Oishi, K. Shiozawa, Y. Tokuda, and S. Satoh, Simulation Study on Comparison Between Metal Gate and Polysilicon Gate for Sub-Quarter-Micron MOS-FET's, 1999, vol. 20, pp. 632-634.
4. E. Josse and T. Skotnicki, "Polysilicon gate with depletion-or-metallic gate with buried channel: what evil worse?," in IEDM Tech. Dig., 1999, pp. 661-664.
5. R. Li and Q. Xu, "Damascene W/TiN gate MOSFETs with improved performance for 0.1μm regime," IEEE Trans. Electron devices, to be published.
6. S. Matsuda, H. Yamakawa, A. Azuma, and Y. Toyoshima, "Performance improvement of metal gate CMOS technologies," in VLSI Tech. Dig., 2001, pp. 63-64.
7. B. Cheng, B. Maiti, S. Samavedam, J. Grant, B. Taylor, P. Tobin, and J. Mogab, "Metal gates for advanced Sub-80-nm SOI CMOS technology," in IEEE Int. SOI Conf, 2001, pp. 91-92.
8. C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, "A comparative study of advanced MOSFET concepts," IEEE Trans. Electron Devices, vol. 43, pp. 1742-1753, Oct. 1996.
9. ISE TCAD 8.0, Integrated Systems Engineering, Zurich.
10. DESSISe Manuals, ISE TCAD 8.0, Integrated Systems Engineering, Zürich, Switzerland.
11. Y. Taur, C. H. Wann, and D. J. Frank, "25 nm CMOS design considerations," in IEDM Tech. Dig., 1998, pp. 789-192.
12. Y. Taur and E. J. Nowak, "CMOS devices below 0.1 μm: How high will performance go?" in IEDM Tech. Dig., 1997, pp. 215-218.