A DVS embedded power management for high efficiency integrated SoC in UWB system

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 11, 2010, Pages 2227-2238

  Lee, Yu Huei ^a   Yang, Yao Yi ^a   Chen, Ke Horng ^a   Lin, Ying Hsi ^b   Wang, Shih Jung ^a   Zheng, Kuo Lin ^a   Chen, Po Fung ^a   Hsieh, Chun Yu ^a   Ke, Yu Zhou ^a   Chen, Yi Kuang ^b   Huang, Chen Chih ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b REALTEK SEMICONDUCTOR CORP   (Taiwan)

Author keywords

DC DC converter; dynamic voltage scaling; low voltage operation; power conversion efficiency; power management; transient response; UWB system

Indexed keywords

DYNAMIC VOLTAGE SCALING; LOW-VOLTAGE OPERATION; POWER CONVERSION EFFICIENCIES; POWER MANAGEMENTS; TRANSIENT RESPONSE; UWB SYSTEM;

BROADBAND NETWORKS; CONVERSION EFFICIENCY; DC-DC CONVERTERS; ENERGY MANAGEMENT; HVDC POWER TRANSMISSION; MANAGEMENT; PROGRAMMABLE LOGIC CONTROLLERS; SPACE OPTICS; SYSTEM STABILITY; TRANSIENT ANALYSIS;

VOLTAGE STABILIZING CIRCUITS;

EID: 77958532564     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2063610     Document Type: Conference Paper

References (24)

1. H.-W. Huang, K.-H. Chen, and S.-Y. Kuo, "Dithering skip modulation, width and dead time controllers in highly efficient DC-DC converters for system-on-chip applications," IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2451-2465, Nov. 2007.
2. K.-H. Chen, C.-J. Chang, and T.-H. Liu, "Bidirectional current-mode capacitor multipliers for on-chip compensation," IEEE Trans. Power Electron., vol. 23, no. 1, pp. 180-188, Jan. 2008.
3. G. Patounakis, Y. W. Li, and K. L. Shepard, "A fully integrated on-chip DC-DC conversion and power management system," IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 443-451, Mar. 2004.
4. M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, and P. Palmer, "A 3 GHz switching DC-DC converter using clock-tree charge-recycling in 90 nm CMOS with integrated output filter," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 532-533.
5. C.-Y. Hsieh and K.-H. Chen, "Adaptive Pole-Zero Position (APZP) technique of regulated power supply for improving SNR," IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2949-2963, Nov. 2008.
6. F.-F. Ma, W.-Z. Chen, and J.-C. Wu, "A monolithic current-mode buck converter with advanced control and protection circuit," IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1836-1846, Sep. 2007.
7. M. D. Mulligan, B. Broach, and T. H. Lee, "A 3 MHz low-voltage buck converter with improved light load efficiency," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 528-529.
8. I. Doms, P. Merken, C. Van Hoof, and R. P. Mertens, "Capacitive power management circuit for micropower thermoelectric generators with a 1.4 μA controller," IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2824-2833, Oct. 2009.
9. Y.-H. Lee, S.-J. Wang, Y.-Y. Yang, K.-L. Zheng, P.-F. Chen, C.-Y. Hsieh, Y.-Z. Ke, K.-H. Chen, Y.-K. Chen, C.-C. Huang, and Y.-H. Lin, "A DVS embedded power management for high efficiency integrated SoC in UWB system," in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 321-324.
10. J. Kwong, Y. K. Ramadass, N. Verma, and A. P. Chandrakasan, "A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 115-126, Jan. 2009.
11. M.-H. Huang, P.-C. Fan, and K.-H. Chen, "Low-ripple and dual-phase charge pump circuit regulated by switched-capacitor-based bandgap reference," IEEE Trans. Power Electron., vol. 24, no. 5, pp. 1161-1172, May 2009.
12. P. Favrat, P. Deval, and M. J. Declercq, "A high-efficiency CMOS voltage doubler," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, Mar. 1998.
13. S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, "A self-tuning DVS processor using delay-error detection and correction," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792-804, Apr. 2006.
14. S. Xiao, W. Qiu, G. Miller, T. X. Wu, and I. Batarseh, "An active compensator scheme for dynamic voltage scaling of voltage regulators," IEEE Trans. Power Electron., vol. 24, no. 1, pp. 307-311, Jan. 2009.
15. M. E. Sinangil, N. Verma, and A. P. Chandrakasan, "A reconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3163-3173, Nov. 2009.
16. P. Hazucha, S. T. Moon, G. Schrom, F. Paillet, D. Gardner, S. Rajapandian, and T. Karnik, "High voltage tolerant linear regulator with digital control for biasing of integrated DC-DC converters," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 66-73, Jan. 2007.
17. Y.-H. Lin, K.-L. Zheng, and K.-H. Chen, "Power MOSFET array for smooth pole tracking in LDO regulator compensation," IEEE Trans. Power Electron., vol. 23, no. 5, pp. 2421-2427, Sep. 2008.
18. R. J. Milliken, J. Silva-Martínez, and E. Sanchez-Sinencio, "Full on-chip CMOS low-dropout voltage regulator," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 9, pp. 1879-1890, Sep. 2007.
19. S. O. Cannizzaro, A. D. Grasso, R. Mita, G. Palumbo, and S. Pennisi, "Design procedures for three-stage CMOS OTAs with nested-Miller compensation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 5, pp. 933-940, May 2007.
20. X. Fan, C. Mishra, and E. Sanchez-Sinencio, "Single Miller capacitor compensated multistage amplifiers for large capacitive load applications," in Proc. IEEE Int. Symp. Circuits and Systems, May 2004, vol. 1, pp. 23-26.
21. G. A. Rincon-Mora, "Active capacitor multiplier in Miller-compensated circuits," IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 26-32, Jan. 2000.
22. C.-H. Lin, K.-H. Chen, and H.-W. Huang, "Low-dropout regulators with adaptive reference control and dynamic push-pull techniques for enhancing transient performance," IEEE Trans. Power Electron., vol. 24, no. 4, pp. 1016-1022, Apr. 2009.
23. M. Al-Shyoukh, H. Lee, and R. Perez, "A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation," IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732-1742, Aug. 2007.
24. R. G. Carvajal, J. Ramirez-Angulo, A. J. Lopez-Martin, A. Torralba, J. A. Gomez Galan, A. Carlosena, and F. Munoz Chavero, "The flipped voltage follower: A useful cell for low-voltage low-power circuit design," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp. 1276-1291, Jul. 2005.