Design procedures for three-stage CMOS OTAs with nested-Miller compensation

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 5, 2007, Pages 933-940

  Cannizzaro, Salvatore Omar ^a   Grasso, Alfio Dario ^a   Mita, Rosario ^a   Palumbo, Gaetano ^a   Pennisi, Salvatore ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

CMOS; Multistage amplifiers; Nested Miller compensation; Operational transconductance amplifiers (OTAs)

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC CURRENTS; ELECTRIC NETWORK TOPOLOGY; OPERATIONAL AMPLIFIERS; TRANSCONDUCTANCE;

ANALOG KNOWLEDGE-BASED COMPUTER-AIDED DESIGN; MULTISTAGE AMPLIFIERS; NESTED-MILLER FREQUENCY COMPENSATION; OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTAS);

CMOS INTEGRATED CIRCUITS;

EID: 34248632007     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.895520     Document Type: Article

References (23)

1. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signals Processing. New York: Wiley, 1986.
2. P. Allen and D. Holberg, CMOS Analog Circuit Design. New York: Holt Rinehart and Winston, 1987.
3. K. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems. New York: Mc Graw-Hill, 1994.
4. G. Palmisano, G. Palumbo, and S. Pennisi, "Design procedures for two-stage CMOS OTAs: A tutorial," Anal. Integr. Circuits Signal Process., vol. 27, no. 3, pp. 179-189, May 2001.
5. J. Mahattanakul, "Design procedure for two-stage operational amplifiers employing current buffer," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 11, pp. 766-770, Nov. 2005.
6. F. Op'T EEynde, P. Ampe, L. Verdeyen, and W. Sansen, "A CMOS large-swing low-distortion three-stage Class-AB power amplifier," IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 265-273, Feb. 1990.
7. S. Pernici, G. Nicollini, and R. Castello, "A CMOS low distortion fully differential power amplifier with double nested-Miller compensation," IEEE J. Solid-State Circuits, vol. 28, no. 7, pp. 758-763, Jul. 1993.
8. R. Eschauzier and J. Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers. Boston, MA: Kluwer Academic, 1995.
9. K. Leung and P. Mok, "Analysis of multistage amplifier-frequency compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. vol. 48, no. 9, pp. 1041-1056, Sep. 2001.
10. R. Eschauzier and J. Huijsing, "A 100-MHz 100-dB operational amplifier with multipath nested-Miller compensation," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992.
11. F. You, S. Embabi, and E. Sanchez-Sinencio, "Multistage amplifier topologies with nested Gm-C compensation," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2000-2011, Dec. 1997.
12. K. Leung and P. Mok, "Nested-Miller compensation in low-power CMOS design," IEEE Trans. Circuits Syst. II, vol. 48, no. 4, pp. 388-394, Apr. 2001.
13. G. Palumbo and S. Pennisi, "Design methodology and advances in nested-Miller compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 7, pp. 893-903, Jul. 2002.
14. X. Fan, C. Mishra, and E. Sanchez-Sinencio, "Single Miller capacitor frequency compensation technique for low-power multistage amplifiers," IEEE J. Solid-State Circuits, vol. 38, pp. 1735-1738, Oct. 2003.
15. X. Peng and W. Sansen, "AC boosting compensation scheme for low-power multistage amplifiers," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2074-2077, Nov. 2004.
16. A. D. Grasso, G. Palumbo, and S. Pennisi, "Three-stage CMOS OTA for large capacitive loads with efficient frequency compensation scheme," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp. 1044-1048, Oct. 2006.
17. A. D. Grasso, G. Palumbo, and S. Pennisi, "Analytical comparison of frequency compensation techniques in three-stage amplifiers," Int. J. Circuit Theory Appl., to be published.
18. A. D. Grasso, D. Marano, G. Palumbo, and S. Pennisi, "Improved reversed nested-Miller frequency compensation technique with voltage buffer and resistor," IEEE Trans. Circuits Syst. II, Exp. Briefs, to be published.
19. W. Aloisi, G. Giustolisi, and G. Palumbo, "Design and comparison of very low-voltage CMOS output stages," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8, pp. 1545-1556, Aug. 2005.
20. H. Yang and D. Allstot, "Considerations for fast settling operational amplifiers," IEEE Trans. Circuits Syst., vol. 37, no. 3, pp. 326-334, Mar. 1990.
21. R. Mita, G. Palumbo, and S. Pennisi, "Well-defined design procedure for a three-stage CMOS OTA," in Proc. IEEE ISCAS, Kobe, Japan, 2005, vol. 3, pp. 2579-2582.
22. P. R. Kinget, "Device mismatch and tradeoffs in the design on analog circuits," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212-1224, Jun. 2005.
23. G. Giustolisi and G. Palumbo, "An approach to test the open-loop parameters of feedback amplifiers," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 1, pp. 70-75, Jan. 2002.