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Volumn , Issue , 2009, Pages 321-324

A DVS embedded power management for high efficiency integrated SoC in UWB system

Author keywords

[No Author keywords available]

Indexed keywords

COMPENSATION CIRCUITS; HANDOVER TECHNIQUES; HIGH EFFICIENCY; LOOP GAINS; LOW-VOLTAGE; MULTI-STAGE AMPLIFIERS; ON CHIPS; POWER CONDITIONING; POWER CONVERSION EFFICIENCIES; POWER MANAGEMENTS; PRE-REGULATOR; PWM CONTROLLERS; SELF BIASING; SUPPLY VOLTAGES; SYSTEM-ON-CHIP APPLICATIONS; TRANSIENT RESPONSE; ULTRAWIDEBAND SYSTEMS; UWB SYSTEM;

EID: 76249089740     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2009.5357159     Document Type: Conference Paper
Times cited : (5)

References (5)
  • 1
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    • Jan
    • Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, and Anantha P. Chandrakasan, A 65nm Sub-Vt Microcontroller with. Integrated SRAM and Switched. Capacitor DC-DC Converter, IEEE J. Solid-State Circuits, vol.44, no 1, pp. 115-126, Jan. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.1 , pp. 115-126
    • Kwong, J.1    Ramadass, Y.K.2    Verma, N.3    Chandrakasan, A.P.4
  • 2
    • 51749109057 scopus 로고    scopus 로고
    • Dithering skip modulation, width and dead time controllers in highly efficient DCDC converters for system-on-chip applications
    • Nov
    • Hong-Wei Huang, Ke-Homg Chen, and Sy-Yen Kuo, Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DCDC Converters for System-on-chip Applications, in IEEE Journal of Solid-State Circuits, pp. 2451 -2465, Nov. 2007.
    • (2007) IEEE Journal of Solid-State Circuits , pp. 2451-2465
    • Huang, H.-W.1    Chen, K.-H.2    Kuo, S.-Y.3
  • 3
    • 34548817018 scopus 로고    scopus 로고
    • A 3MHz low voltage buck converter with improved light load efficiency
    • Feb
    • Michael. D. Mulligan, Bill Broach, and Thomas H. Lee, A 3MHz LowVoltage Buck Converter with Improved Light Load Efficiency, IEEE ISSSC Dig. Tech. Papers, pp. 528-529, Feb. 2007.
    • (2007) IEEE ISSSC Dig. Tech. Papers , pp. 528-529
    • Mulligan, M.D.1    Broach, B.2    Lee, T.H.3
  • 4
    • 33846197039 scopus 로고    scopus 로고
    • High. voltage tolerant linear regulator with digital control for biasing of integrated DC-DC converters
    • Jan
    • Peter Hazucha, Sung Tae Moon, Gerhard. Schrom, Fabrice Paillet, Donald Gardner, Saravanan Rajapandian, and Tanay Karnik, High. Voltage Tolerant Linear Regulator With Digital Contra! for Biasing of Integrated DC-DC Converters, IEEE J. Solid-State Circuits, vol.42, no 1, pp. 66-73, Jan. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.1 , pp. 66-73
    • Hazucha, P.1    Moon, S.T.2    Schrom, G.3    Paillet, F.4    Gardner, D.5    Rajapandian, S.6    Karnik, T.7
  • 5
    • 57349168519 scopus 로고    scopus 로고
    • Power MOSFET array for smooth pole tracking in LDO regulator compensation
    • Sept
    • Yung-Hsin Lin, Kuo-Lin Zheng, and Ke-Homg Chen, Power MOSFET Array for Smooth Pole Tracking in LDO Regulator Compensation, in IEEE Transaction on Power Electronics, pp. 2421-2427, Sept. 2008.
    • (2008) IEEE Transaction on Power Electronics , pp. 2421-2427
    • Lin, Y.-H.1    Zheng, K.-L.2    Chen, K.-H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.