A low-power RISC microprocessor using dual PLLs in a 0.13 μm SOI technology with copper interconnect and low-k BEOL dielectric

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 148-149+137

  Geissler, Stephen ^a   Appenzeller, David ^a   Cohen, Erwin ^a   Charlebois, Steven ^a   Kartschoke, Paul ^a   McCormick, Peter ^a   Rohrer, Norman ^a   Salem, Gerard ^a   Sandon, Peter ^a   Singer, Bruce ^a   Von Reyn, Timothy ^a   Zimmerman, Jeffrey ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DIELECTRIC MATERIALS; DIODES; LOGIC CIRCUITS; MOSFET DEVICES; PHASE LOCKED LOOPS; REDUCED INSTRUCTION SET COMPUTING; RESISTORS; SHIFT REGISTERS; SILICON ON INSULATOR TECHNOLOGY; SWITCHING; VARIABLE FREQUENCY OSCILLATORS;

FREQUENCY SWITCHING;

MICROPROCESSOR CHIPS;

EID: 0036116742     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 480 MHz RISC microprocessor in a 0.12 μm leff CMOS technology
2. High performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
3. A high-speed, low-power clock generator for a microprocessor application
4. CMOS technology: Present and future