The first MAJC microprocessor: A dual CPU system-on-a-chip

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 11, 2001, Pages 1609-1616

  Kowalczyk, Andre ^a,b   Adler, Victor ^b   Amir, Chaim ^a,b   Chiu, Frank ^b   Chng, Choon Ping ^a,b   De Lange, Willem J ^a,b   Ge, Yuefei ^b   Ghosh, Subhendra ^a,b   Hoang, Tan Canh ^b   Huang, Baoqing ^b   Kant, Shree ^b   Kao, Y S ^b   Khieu, Cong ^b   Kumar, Suresh ^b   Lee, Lan ^b   Liebermensch, Avi ^b   Liu, Xin ^b   Malur, Naveen G ^b   Martin, Albert A ^a,b   Ngo, Hiep ^a,b   Oh, Sung Hun ^a,b   Orginos, Ioannis ^b   Shih, Lorraine ^b   Sur, Balmiki ^b   Tremblay, Marc ^a,b   Tzeng, Allan ^a,b   Vo, Dan ^b   Zambare, Sanjay ^b   Zong, Jin ^b   more..

^a IEEE   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

Clock distribution; CMOS integrated circuits; CMP; Computer architecture; Coupling noise; Flip flops; High speed integrated circuits; Logic design; Microprocessors

Indexed keywords

CLOCK DISTRIBUTION; COUPLING NOISE; FLIP CHIP ASSEMBLY TECHNOLOGY;

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COPPER; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; TRANSISTORS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 6644227176     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.962280     Document Type: Article

References (6)

1. The MAJC architecture: A synthesis of parallelism and scalability
2. First-generation MAJC dual microprocessor
3. The ultra-SPARC port architecture
4. A third-generation SPARC V9 64-b microprocessor
5. A new family of semi-dynamic and dynamic flip-flops with embedded logic for high-performance processors
6. eff CMOS technology with copper interconnects