On-chip segmented bus: A self-timed approach

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 216-220

  Seceleanu, Tiberiu ^a   Plosila, Juha ^a   Liljeberg, Pasi ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUSES; INTEGRATED CIRCUIT DESIGN; SYSTEM-ON-CHIP;

BUS BASED SYSTEMS; BUS STRUCTURES; DESIGN RULES; DIFFERENT SPEED; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; INTER-MODULE; SEGMENTED BUS ARCHITECTURE; SYSTEM ON CHIP DESIGN;

MICROPROCESSOR CHIPS;

EID: 0344841127     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158059     Document Type: Conference Paper

References (15)

1. ARM Limited. AMBA Specification (Rev 2.0), 1999.
2. American National Standards Institution. Small Computer System Interface (SCSI), 1986.
3. W.J,Bainbridge and SB Furber. Asynchronous Macrocell Interconnect Using MARBLE. In Proceedings of the 4th Intemationai Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98) San Diego, CA, March 30 - April 2, 1998.
4. D. M. Chapiro. Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, Standford University, 1984.
5. J. Y Chen et al. Segmented Bus Design for Low-Power Systems. IEEE Transactions On Very Large Scale Integration Systems, Vol. 7, No. 1, March 1999, pp. 25-29
6. W.J. Dally and J.W. Poulton. Digital System Engineering. Cambridge University Press 1998.
7. S. Hauck. Asynchronous Design Methodologies: An Overview Proceedings of the IEEE, Vol. 83, No. 1, pp.69-93,January 1995.
8. J. Jeon, K. Choi, An Effective Synthesis Algorithm for Partitioned Bus Architecture. Institute of Electrical Engineers, Electronics Letters, Vol. 35, No. 6, 18 March 1999, pp. 440-441.
9. C, Katsinis. A Segmented-Shared-Bus Multicomputer Architecture. Ninth International Conference on Parallel and Distributed Computing and Systems (PDCS'97),Washington, DC, 1997.
10. G. Kotsis. fnterconnection Topologies for Parallel Processing Systems. PARS Mitteilungen, No. 11, June, 1993, pages 1-6.
11. R.Krishnamurti, E.Ma. An Approximation Algorithm for Scheduling Tasks on Varying Partition Sizes in Partitionable Multiprocessor Systems. IEEETrans. Comput., Vol.4l pp.1572-1579, Dec.I992.
12. S. Lee and K. Choi Partitioned-bus architecture synthesis based on data transfer model. The Sixth Asia Pacific Conference on Chip Design Language (APCHDL'99), Japan, October 6-8, 1999
13. I. Ouveysi, A. Wirth. On Design Of A Survivable Network Architecture For Dynamic Routing: Optimal Solution Strategy And An Efficient Heurisäc. European Journal of Operational Research 117 (1999) 30-44.
14. C.-H.Yeh, B, Parhami. Design of High-Performance Massively Par-allel Architectures Under Pin Limitations and Non-Uniform Propagation Delay. Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis (pAs '97).
15. A. Zitouni et al. Design of an Asynchronous VME bus Controller for Heterogeneous systems. Dedicated Systems Magazine - 2000 Q3 (http://www.dedicated-systems.com).