Interfacing synchronous and asynchronous modules within a high-speed pipeline

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 5, 2000, Pages 573-583

  Sjogren, Allen E ^b   Myers, Chris J ^a,c  

^a IEEE   (United States)

^b Smurfit Stone Container Corporation   (United States)

^c Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS PIPELINE; METASTABILITY; RING OSCILLATORS; STOPABLE CLOCKS; SYNCHRONOUS PIPELINE;

COMPUTER SIMULATION; ELECTRIC POTENTIAL; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; OSCILLATORS (ELECTRONIC); PIPELINE PROCESSING SYSTEMS; TEMPERATURE; TIMING CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034289978     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.894162     Document Type: Article

References (13)

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