Automatic synthesis of Near-Threshold Circuits with fine-grained performance tunability

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2010, Pages 401-406

  Kakoee, Mohammad Reza ^a   Sathanur, Ashoka ^b   Pullini, Antonio ^b   Huisken, Jos ^b   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b IMEC ^*  (Switzerland)

Author keywords

Algorithms; Design; Performance

Indexed keywords

AUTOMATIC SYNTHESIS; DESIGN MARGIN; DUAL-VDD; HIGHLY SENSITIVE; LEVEL SHIFTER; NOISE IMMUNITY; PERFORMANCE; PERFORMANCE IMPROVEMENTS; PERFORMANCE TARGETS; POST-SILICON; STATIC AND DYNAMIC; SUBTHRESHOLD; SUPPLY VOLTAGES; THRESHOLD CIRCUITS; THRESHOLD OPERATION; TUNABILITIES; ULTRA LOW ENERGY;

POWER ELECTRONICS; THRESHOLD ELEMENTS; THRESHOLD VOLTAGE;

DESIGN;

EID: 77957938536     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1840845.1840934     Document Type: Conference Paper

References (24)

1. Bo Zhai et.al, "Theoretical and Practical Limits of Dynamic Voltage Scaling," ACM/IEEE DAC, pp. 868-873, USA, 2004.
2. R. G. Dreslinski et.al, "Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits," Proceedings of the IEEE, vol. 98, no. 2, pp. 253-266, February 2010
3. Markovic, D. et.al, "Ultralow-Power Design in Near-Threshold Region," Proceedings of the IEEE, vol. 98, no. 2, pp. 237-252, February 2010.
4. Bo Zhai, et.al, "Energy efficient near-threshold chip multi-processing," ACM ISLPED, pp. 32-37, USA, 2007.
5. R. Dreslinski, et.al, "An energy efficient parallel architecture using near threshold operation," IEEE PACT, pp. 175-185, Romania, 2007.
6. B. Calhoun, A. Wang and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, September 2005.
7. David Bol, et. al, "Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic," ACM ISLPED, pp. 3-8, USA, 2009.
8. David Bol, et.al, "Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits," ACM ISLPED, pp. 21-26, USA, 2009.
9. S. Hanson, et.al, "Exploring variability and performance in a sub-200-mV processor," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 881-891, April 2008.
10. Mingoo Seok, et.al, "Optimal technology selection for minimizing energy and variability in low voltage applications," ACM ISLPED, pp. 9-14, USA, 2008.
11. N. Verma, J. Kwong, A. P. Chandrakasan, "Nanometer MOSFET variation in minimum energy subthreshold circuits," IEEE Transactions on Electron Devices, vol.55, no. 1, pp. 163-174, January 2008.
12. R. Gonzalez, B. M. Gordon, M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, August 1997.
13. H. Soeleman and k. Roy, "Ultra-low power digital subthreshold logic circuits," IEEE ISLPED, pp. 94-96, USA, 1999.
14. A. Wang, A. Chandrakasan, "A 180mV FFT processor using subthreshold circuit techniques," IEEE ISSCC, pp. 292-295, USA, 2004.
15. B. Zhai, et.al, "A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency," IEEE VLSI-Symp, pp.154-155, USA, 2006.
16. C. Kim, H. Soeleman, K. Roy, "Ultra-Low-Power DLMS Adaptive Filter for Hearing Aid Applications," IEEE Transactions on VLSI Systems, vol. 11, no. 6, pp. 1058-1067, December 2003.
17. Ali Keshavarzi, et.al, "Technology scaling behavior of optimum reverse body bias for Standby leakage power reduction in CMOS IC's," ACM ISLPED, pp. 252-254, USA, 1999.
18. Yu Pu, et.al, "An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply," IEEE ISSCC, pp. 146-147, USA, 2009.
19. S. Sakiyama et.al, "An On-Chip High-Efficiency and Low-Noise DC/DC Converter Using Divided Switches with Current Control Technique," IEEE ISSCC, pp. 156-158, USA, 1999.
20. Siyuan Zhou, and Gabriel, "A High Efficiency, Soft Switching DC-DC Converter With Adaptive Current-Ripple Control for Portable Applications," IEEE Transactions on Circuits and Systems, vol. 53, no. 4, pp. 319-323, April 2006.
21. T Hirose, T Asai, and Y Amemiya, "Power-supply circuits for ultralow-power subthreshold MOS-LSIs," IEICE Electronics Express, vol. 3, no. 22, pp. 464-468, November 2006.
22. B. Nezamfar et.al, "Energy-Performance Tunable Logic," IEEE CICC, pp. 183-186, USA, 2009.
23. B. Zhai, S. Pant, et.al, "Energy efficient subthreshold processor design," IEEE Transactions on VLSI Systems, vol. 17, no. 8, pp. 1127-1137, August 2009.
24. Michael Keating, David Flynn, Robert Aitken, Alan Gibsons and Kaijian Shi, Low Power Methodology Manual for System on Chip Design, Springer Publications, NewYork, 2007.