3D integration technologies for emerging microsystems

IEEE MTT-S International Microwave Symposium Digest

Volumn , Issue , 2010, Pages 1-4

  Choudhury, Debabani ^a  

^a INTEL CORPORATION   (United States)

Author keywords

3D ICs; 3D integration; 3D packaging; Emerging microsystems

Indexed keywords

3-D ICS; 3-D INTEGRATION; 3D PACKAGING; 3D STACKING; EMERGING MICROSYSTEMS; ENABLING TECHNOLOGIES; INTEGRATED PACKAGING; MICRO-SYSTEM TECHNOLOGIES; MONOLITHIC IC; SMALL FORM FACTORS; WIRELESS SYSTEMS;

APPROXIMATION THEORY; INTEGRATION; MICROSYSTEMS; PACKAGING; TECHNOLOGY;

THREE DIMENSIONAL;

EID: 77957771527     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSYM.2010.5514747     Document Type: Conference Paper

References (27)

1. K. Kahn, "Building the Mobile Tomorrow," Intel Developers Forum, March 2006.
2. M. Niedermayer, et al., "Miniaturization Platform for Wireless Sensor Nodes Based on 3D-packaging Technologies", IPSN'06 Digest, pp.391-397, TN, USA, April 2006.
3. www.e-cubes.org
4. R. Tummala and M. Swaminathan, 'System-On-Package: Miniaturization of the Entire System', McGraw Hill, 2008
5. P. Garrou et al. (Eds), 'Handbook of 3D Integration: technology and Integration of 3D Integrated Circuits', WiIey-VCH, 2008
6. S. EI-Sarawi et al., "A Review of 3-D Packaging Technology" ,pp.2-13, IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, vol.21, No.1, Feb.l998
7. S. Borkar, "3D Integration for Energy Efficient System Design", 2009 IEEE Symposium on VLSI Technology Digest, pp. 58-59, 2009.
8. J.-Q. Lu, "3D Hyperintegration and Packaging Technologies for Micro-Nano Systems," Proceedings of IEEE, vol.97, No.1, pp. 18-30, January 2009.
9. R.S. Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs," Proceedings of IEEE, vol.94, No.6, pp. 1214-1224, June 2006.
10. R. Tummala et al., "Trend from ICs to 3DICs to 3D Systems", 2009 IEEE Custom Integrated Circuits Conference Digest, pp.439-444, CICC 2009
11. M. Rosker et al., "Compound Semiconductor Materials On Silicon (COSMOS)", IEEE CSIC Symposium, 2008
12. T. Kazior et al., "A High Performance Differential Amplifier Through the Direct Monolithic Integration of InP HBTs and Si CMOS on Silicon Substrates", pp.1113-1116, IEEE Int. Microwave Symposium, Boston, MA, 2009
13. Y. Uemoto et al., "GaN Monolithic Inverter IC Using Normallyoff Gate Injection Transistors with Planar Isolation on Si Substrate", 2009 IEEE IEDM Digest, pp.96-98, Dec.2009
14. T.Fukushima et al., "Three-Dimensional Integration Technology Based on Reconfigured Wafer-to-Wafer and Multichip-to-Wafer Stacking Using Self Assembly Method", 2009 IEEE International Electron Devices Meeting, pp.1-4, IEDM 2009
15. F.P.Carson et al., "3-D Stacked Package Technology and Trends", Proceedings of IEEE, vol.97, No.1, pp. 18-30, January 2009.
16. B. Black, "Die Stacking (3D) Microarchitecture", Proc. of 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)
17. T-K Hwang et al., "Board Level Reliability Assessments of Thru-Mold Via Package on Package (TMV™ POP)", Proc. 2009 International Conf. on Electronic Packaging Technology and High Density Packaging, pp.1124-1129, 2009.
18. th Int. Spring Seminar on Electronic Technology, pp.399-405, 2005.
19. B-W. Lee et al., "Chip-Last Embedded Active for System-On Package (SOP)", 2007 Electronics Components and Technology Conference, pp.292-298, 2007.
20. T. Chiang et al., "Effect of Via Separation and Low-K Dielectric Materials on the Thermal Characteristics of Cu- Interconnects", IEEE International Electron Devices Meeting (IEDM] Digest, pp.261-264, 2000.
21. J.-Q. Lu et al., "3D Architecture for Power Delivery to Microprocessors and ASICs", Proc. 3rd Int. Conf. 3D Architect. Semiconductor Integration Packaging, 2006.
22. J. Koo et al., "Integrated Microchannel Cooling for threedimensional Circuit Architectures", ASME J. of Heat Transfer, vol.127, pp.49-58, Jan.2005.
23. H. Jiang, L. Zhu, K. Moon, C. P. Wong, "Low Temperature Carbon Nanotube Film Transfer Via Conductive Polymer Composites", Nanotechnology Vol. 18 (12), Art. #125203,2007.
24. S.K. Lim, "Physical Design for 3D System on Package", IEEE Design and Test of Computers, vo1.22, No.6, pp.532-539, Nov./Dec. 2005.
25. S.Y. Liao, "Towards a New Standard for System-Level Design", Proceedings of the 8th International Workshop on Hardware/Software Co-design, San Diego, CA, 2000.
26. H.S. Lee, "Test Challenges for 3D Integrated Circuits", IEEE Design and Test for Computers, Sept/Oct. 2009
27. th Electronics Packaging Technology Conference, pp.338-340, 2008.