Physical design and technology parameters for vertical system-in-package integration

28th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2005

Volumn 2005, Issue , 2005, Pages 413-419

  Polityko, David Dmitry ^a   Guttowski, Stephan ^b   John, Werner ^b   Reichl, Herbert ^a  

^a TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

^b FRAUNHOFER IZM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

PHYSICAL DESIGNS; SIP TECHNOLOGIES; SYSTEM-IN-PACKAGE INTEGRATION;

ELECTRONICS PACKAGING; ENGINEERING RESEARCH; PRODUCT DESIGN; TECHNOLOGY;

ELECTRONICS ENGINEERING;

EID: 33745433762     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSE.2005.1491064     Document Type: Conference Paper

References (13)

1. International Technology Roadmap for Semiconductors, 2003 edition & 2004 update, http://public.itrs.net/.
2. S.F. Al-Sarawi, D. Abbott, P. Franzon, "A Review of 3-D Packaging Technology", IEEE Transactions On Components, Packaging And Manufacturing Technology - Part B, Vol. 21, No. 1, 1998.
3. Y. Deng, W. Maly, "Physical Design of the 2.5D Stacked System," Int'l Conference on Computer Design 2003. pp. 211-217.
4. R. Ravichandran, J. Minz, M. Pathak, S. Easwar, Sung Kyu Lim, "Physical layout automation for system-on-packages", Electronic Components and Technology 2004. Proceedings, Vol. 1, 2004.
5. St. P. Larcombe, D.J. Prendergast, N.A. Thacker, P.A. Ivey, "Using Genetic Algorithms to Automate System Implementation in a Novel Three-Dimensional Packaging Technology", Int'l Conference on Computer Design, Proceedings, 1996, pp.274-279.
6. IPC, "Design and Assembly Process Implementation for EGAs", IPC-7095A, October 2004.
7. H. Reichl, A. Ostmann, R. Wieland, P. Ramm, "The third dimension in microelectronics packaging", 14th European Microelectronics and Packaging Conference & Exhibition IMAPS, Friedrichshafen, Germany, 2003.
8. Morihiro Kada, "The Dawn of 3D Packaging As System-in-Package (SIP)," IEICE transactions on electronics, Special Issue on Integrated Systems with New Concepts, Vol.E84-C, No. 12, Japan, 2003, p. 1763.
9. I. Ndip, G. Sommer, W. John, H. Reichl, "Characterization of bump arrays at RF/microwave frequencies", Microelectronics Reliability, Vol. 45, 2005.
10. M. Scheffler, "Cost vs. Quality Trade-off for High-Density Packaging of Electronic Systems", Dissertation, Technical Science ETH Zurich, Vol. 14210, 2001.
11. P.A. Sandborn, H. Moreno, "Conceptual Design of Multichip Modules and Systems", Kluwer International Series in Engineering and Computer Science, Kluwer Academic Publisher, January 1994, pp 64-67.
12. Q. Zou, G. Hirmer, G. Xing, H. Xu, "Sol-Gel Derived Lead Free Ferroelectric Thin Films for Embedded Capacitor Applications", IPC/FED International Conference On Embedded Passives, 2004.
13. L. Schaper, S. Spiesshoeffer, "System Architecture Implications of 3-D Interconnect Technologies", Int. Conf. On Advanced Packaging and Systems, Proceedings, 2002.