On scalable spiking ConvNet hardware for cortex-like visual sensory processing systems

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 249-252

  Camunas Mesa L ^a   Perez Carrasco J A ^a   Zamarreno Ramos C ^a   Serrano Gotarredona, T ^a   Linares Barranco, B ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL SIMULATION; CONVOLUTIONAL NEURAL NETWORK; NANO SCALE; PEOPLE RECOGNITION; RETINA CHIP; SENSORY DATA; SIMULATION RESULT; SPIKING NEURAL NETWORKS; UPSCALING; VISUAL SENSORY;

CONVOLUTION; FABRICS; OBJECT RECOGNITION;

NEURAL NETWORKS;

EID: 77956004252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537918     Document Type: Conference Paper

References (43)

1. K. Fukushima, "Visual Feature Extraction by a Multilayered Network of Analog threshold Elements," IEEE Trans. Syst. Sci. and Cybernetics, vol. SSC-5, No. 4, pp. 322-333, Oct. 1969.
2. K. Fukushima and N. Wake, "Handwritten Alphanumeric Character Recognition by the Neocognitron," IEEE Trans. Neural Networks, vol. 2, No. 3, pp. 355-365, May 1991.
3. Y. LeCun and Y. Bengio, "Convolutional Networks for Images, Speech, and Time Series," in The Handbook of Brain Science and Neural Networks, M. Arbib (Ed.), Cambridge, MA: MIT Press, pp. 255-258, 1995.
4. L. Bottou and Y. LeCun, "Graph Transformer Networks for Image Recognition," Proc. oflSI.
5. T. Serre, L. wolf, S. Bileschi, M. Riesenhuber, and T. Poggio, "Robust Object Recognition with Cortex-Like Mechanisms," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 29, No. 3, pp. 411-426, March 2007.
6. Jain V, et al., "Supervised learning of image restoration with convolutional networks," IEEE Int. Conf. Comp.t Vis. (ICCV), 2007.
7. R. Collobert and J. Weston, "A unified architecture for natural language processing: deep neural networks with multitask learning," Proc. Int. Conf. on Machine Learning (ICML 08), pp. 160-167, 2008.
8. R. Hadsell, P. Sermanet, M. Scoffier, A. Erkan, K. Kavackuoglu, U. Muller and Y. LeCun, "Learning Long-Range Vision for Autonomous Off-Road Driving," J. Field Robotics, 26(2)420-144, February 2009.
9. D. S. Ricket, et al., "On the Self-Generation of Electrical Soliton Pulses," IEEE J. Solid-State Circ, vol. 42, No. 8, pp. 1657-1668, Aug. 2007.
10. H. P. Graf, E. Cosatto, L. Bottou, I. Durdanovic, V. Vapnik, "Parallel Support Vector Machines: The Cascade SVM,"
11. S. Thorpe, D. Fize, C. Marlot, "Speed of processing in the human visual system,"Nature 381: 520-2, 1996.
12. S. Thorpe, et al., "SpikeNet: Real-time visual processing with one spike per neuron," Neurocomputing 58-60: 857-64, 2004.
13. R. Serrano-Gotarredona, et al., "A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems," IEEE Trans. Circ. Syst. I, vol. 53, No. 12, pp. 2548-2566, December 2006.
14. R. Serrano-Gotarredona, et al., "On Real-Time AER 2D Convolutions Hardware for Neuromorphic Spike Based Cortical Processing," IEEE Trans. on Neural Networks, vol. 19, No. 7, pp. 1196-1219, July 2008.
15. R. Serrano-Gotarredona, et al., "CAVIAR: A 45k-Neuron, 5M-Synapse, 12G-connects/sec AER Hardware Sensory-Processing-Learning-Actuating System for High Speed Visual Object Recognition and Tracking," IEEE Trans, on Neural Networks, vol. 20, No. 9, pp. 1417-1438, September 2009.
16. P. Lichtsteiner, C. Posch, and T. Delbriick, "A 128x128 120dB 30mW Asynchronous Vision Sensor that Responds to Relative Intensity Change," IEEE J. Solid-State Circ, vol. 43, No. 2, pp. 566-576, Feb. 2008.
17. S. Vangal et al, "An 80-Tile 1.28 TFLOPS Network-on-Chip in 65nm CMOS,"/IEEE ISSCC07, pp. 98-99, Feb. 2007.
18. D. B. Strukov and K. K. Likharev, "CMOL FPGA: a configurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology 16, pp. 888-900, 2005.
19. M. Sivilotti, Wiring Considerations in Analog VLSI Systems with Application to Field-Programmable Networks, Ph.D. Thesis, California Institute of Technology, Pasadena CA, 1991.
20. J. Lazzaro, et al., "Silicon Auditory Processors as Computer Peripherals," IEEE Trans, on Neural Networks, vol 4, pp. 523-528, May 1993.
21. E. Culurciello, et al., "A biomorphic digital image sensor," IEEE J. of Solid-State Circuits, vol. 38, pp. 281-294, 2003.
22. P. F. Ruedi, et al., "A 128x128, pixel 120-dB dynamic-range vision-sensor chip for image contrast and orientation extraction," IEEE J. of Solid-State Circuits, vol. 38, pp. 2325-2333, 2003.
23. S. Chen, and A. Bermak, "Arbitrated Time-To-First Spike CMOS Image Sensor with On-Chip Histogram Equalization," IEEE Trans. VLSI Systems, vol. 15, No. 3, pp. 346-357, March 2007.
24. M. Azadmehr, et al."A foveated AER Imager Chip," Proc. of the IEEE Int. Symp. on Circ. and Syst. (ISCAS2005), pp. 2751-2754, Kobe, Japan, 2005.
25. K. A. Zaghloul and K. Boahen, "Optic nerve signals in a neuromorphic chip,"IEEE Trans. Biomed. Eng, vol. 51, no. 4, pp. 657-675, Apr. 2004.
26. J. Costas-Santos et al., "A contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems," IEEE Trans. Circ. Syst. I, Reg. Papers, vol. 54, no. 7, pp. 1444-1458, July 2007.
27. P. Lichtsteiner, C. Posch, and T. Delbruck, "A 128x128 120dB 30mW Asynchronous Vision Sensor that Responds to Relative Intensity Change," IEEE J. Solid-State Circuits, vol. 43, No. 2, pp. 566-576, Feb. 2008.
28. G. Cauwenberghs, et al., "An analog VLSI Chip with Asynchronous Interface for Auditory Feature Extraction,"IEEE Trans. Circ. Syst, vol. 45, pp. 600-606, May 1998.
29. Chicca et al., "A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity," IEEE Trans. Circ. Syst. Parti, vol. 54, No. 5, pp. 981-993, May 2007.
30. M. Oster, et al., "Quantification of a spike-based winner-take-all VLSI network,"IEEE Trans. Circ. Syst. 1, vol. 55, No. 10, pp. 3160-69, 2008.
31. T. Teixeira, et al., "Event-Based Imaging with Active Illumination in Sensor Networks," Proc. IEEE Int. Symp. Circ. Syst, pp. 644-647, ISCAS 2005.
32. P. Vernier, et al., "An integrated cortical layer for orientation enhancement," IEEE J. solid-State Circ, vol. 32, No. 2, pp. 177-186, Feb. 1997.
33. T. Y. W. Choi, et al., "Neuromorphic implementation of orientation hypercolumns,"/IEEE Trans. Circ. Syst. I, vol. 52, No. 6, pp. 1049-60, 2005.
34. T. Serrano-Gotarredona, et al., "AER image filtering architecture for vision processing systems," IEEE Trans. Circ. Syst. II, Analog Dig. Signal Proc, vol. 46, No. 9, pp. 1064-1071, Sep. 1999.
35. L. Camunas-Mesa, et al., "Fully digital AER convolution chip for vision processing," Proc. 2008 IEEE Int. symp. Circ. & Syst. (ISCAS08), pp. 652-655, May 2008.
36. K. Boahen, "Point-to-Point Connectivity Between Neuromorphic Chips Using Address Events," IEEE Trans. Circ. Sys. II, vol. 47, No. 5, pp. 416-434, 2000.
37. Delorme A, et al., "Networks of integrate-and-fire neurons using Rank Order Coding B: Spike timing dependent plasticity and emergence of orientation selectivity,"Neurocomputing 38-40, pp. 539-45, 2001.
38. J. A. Pérez-Carrasco, et al., "On the Computational Power of AER Vision Processing Hardware," Proc. Int. Conf. Circ. Design & Integ Syst, 2007.
39. D. B. Strukov, et al., "The Missing Memristor Found," Nature, vol. 453, pp. 80-83, 1 May 2008.
40. D. B. Strukov and K. K. Likharev, "CMOL FPGA: a configurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology 16, pp. 888-900, 2005.
41. B. Linares-Barranco and T. Serrano-Gotarredona, "Memristance can explain Spike-Time-Dependent-Plasticity in Neural Synapses," Nature Precedings 〈http://hdl.handle.net/10101/npre.2009.3010.1〉 31st March, 2009.
42. B. Linares-Barranco and T. Serrano-Gotarredona, "Exploiting Memristance in Adaptive Asynchronous Spiking Neuromorphic Nanotechnology Systems," Proc. IEEE NANO, July 2009.
43. J. A. Pérez-Carrasco, et al. , "On Neuromorphic Spiking Architectures for Asynchronous STDP Memristive Systems," IEEE ISCAS 2010.