Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting

IET Circuits, Devices and Systems

Volumn 4, Issue 3, 2010, Pages 207-217

  Yu, G ^a   Wang, Y ^a   Yang, H ^a   Wang, H ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ACQUISITION MODES; ALL DIGITAL PHASE LOCKED LOOP; ALL-DIGITAL PLL; CALIBRATION BLOCK; DIGITALLY CONTROLLED OSCILLATORS; ESTIMATION ERRORS; HARDWARE DESCRIPTION LANGUAGES; HIGH-SPEED INTEGRATED CIRCUITS; INHERENT CHARACTERISTICS; LOOP PARAMETERS; LOOP-BANDWIDTH CONTROL; MODE-SWITCHING; MODELSIM; SETTLING TIME; SIMULATION RESULT; TRACKING MODE; WIRELESS COMMUNICATIONS;

CALIBRATION; COMPUTER HARDWARE DESCRIPTION LANGUAGES; OPTICAL COMMUNICATION; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; TUNING; WIRELESS TELECOMMUNICATION SYSTEMS;

ESTIMATION;

EID: 77955721061     PISSN: 1751858X     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cds.2009.0173     Document Type: Article

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