Fast-lock hybrid PLL combining fractional-N and integer-N modes of differing bandwidths

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 2, 2008, Pages 379-389

  Woo, Kyoungho ^a,b   Liu, Yong ^a,b,c   Nam, Eunsoo ^a,d   Ham, Donhee ^a,b  

^a IEEE

^b HARVARD UNIVERSITY   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Charge pump phase locked loops; Fractional N frequency synthesizers; Integer N frequency synthesizers; Phase locked loops

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; FREQUENCY SYNTHESIZERS; SWITCHING;

CONVENTIONAL VARIABLE-BANDWIDTH; DIGITAL PROTOCOL; PLL APPLICATIONS;

PHASE LOCKED LOOPS;

EID: 38849159085     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.914281     Document Type: Article

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