A fast-settling PLL frequency synthesizer with direct frequency presetting

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Kuang, Xiaofei ^a   Wu, Nanjian ^a  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; CMOS INTEGRATED CIRCUITS; PHASE LOCKED LOOPS; PHASE NOISE; TEMPERATURE MEASUREMENT;

FREQUENCY PRESETTING; OUTPUT FREQUENCY; SETTLING TIME;

FREQUENCY SYNTHESIZERS;

EID: 33947229904     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. Lee and B. Kim, "A Low Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control," IEEE J. Solid-State Circuits, vol. 35, pp. 1137-1145, Aug., 2000.
2. C. Y. Yang and S. I. Liu, "Fast Settling Frequency Synthesizer with a Discriminator-Aided Phase Detector," IEEE J. Solid-State Circuits, vol. 35, pp. 1445-1452, Oct., 2000.
3. Tom A. D. Riley, Miles A. Copeland and Tad A. Kwasniewski, "Delta-Sigma Modulation in Fractional-N Frequency Synthesis," IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May, 1993.
4. A. M. Fahim and M. I. Elmasry, "A Wideband Sigma-Delta Phase-Locked-Loop Modulator for Wireless Applications," T. Circuits and Systems II, vol. 50, pp. 53-62, Feb., 2003.