Feed-forward compensation technique for all digital phase locked loop based synthesizers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3209-3212

  Chaivipas, Win ^a   Matsuzawa, Akira ^a   Oh, Philipus Chandra ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ERROR COMPENSATION; FEEDFORWARD CONTROL; MATHEMATICAL MODELS; PARAMETER ESTIMATION;

FEED-FORWARD COMPENSATION;

FREQUENCY SYNTHESIZERS;

EID: 34247137732     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. S. M. Shahruz, "A Low-Noise and Fast-Locking Phase-Locked Loop", Proc. of the American Control Conference, Vol. 3 pp. 2407-2412, Jun. 2003.
3. J. Dunning, G. Garcia, J. Lundberg and E. Nuckolls, "An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors", IEEE J. Solid-State Circuits, vol. 30, pp. 412-422, Apr. 1995.
4. P. Chen, C. Chung, and C. Lee, "An All-Digital PLL with Cascaded Dynamic Phase Average Loop for Wide Multiplication Range Applications," Proc. ISCAS, pp. 4875-4878, May 2005.
5. R. B. Staszewski and P. T. Balsar, "Phase-Domain All-Digital Phase-Locked Loop," IEEE Trans. Circuits and Systems II, Vol. 52, pp. 159-163, Mar. 2005.
6. A. Kajiwara and M. Nakagawa, "A New PLL Frequency Synthesizer with High Switching Speed," IEEE Trans. Vehicular Technology, Vol. 41, pp. 407-413, Nov. 1992.
7. B. Zhang, and P. Allen "Feed-Forward Compensated High Switching Speed Digital Phase-Locked Loop Frequency Synthesizer", Proc. ISCAS, Vol.4, pp. 371-374, Jun. 1999.