A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2006, Pages 105-108

  Sheng, Duo ^a   Chung, Ching Che ^a   Lee, Chen Yi ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL ARITHMETIC; DIGITAL LIBRARIES; ENERGY MANAGEMENT; INTEGRATED CIRCUITS; INTELLECTUAL PROPERTY; LAWS AND LEGISLATION; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; PROGRAMMABLE LOGIC CONTROLLERS; TELECOMMUNICATION;

ALL DIGITAL PHASE-LOCKED LOOP; ASIA-PACIFIC; CELL LIBRARIES; DIGITALLY CONTROLLED-OSCILLATOR; HARDWARE DESCRIPTION LANGUAGE; HIGH RESOLUTIONS; INTELLECTUAL PROPERTY (IP); LOCK-IN; LOW POWERS; POWER CONSUMPTION; REFERENCE CLOCKS; SOC APPLICATIONS; SYSTEM-LEVEL POWER MANAGEMENT; SYSTEM-ON-CHIP APPLICATIONS; TIME-TO-DIGITAL-CONVERTER;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 50249119149     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2006.342325     Document Type: Conference Paper

References (10)

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