메뉴 건너뛰기




Volumn , Issue , 2008, Pages 2625-2628

Fast frequency acquisition all-digital PLL using PVT calibration

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC COMPOUNDS; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; DIGITAL ARITHMETIC; FORECASTING; OSCILLATORS (ELECTRONIC); SENSORS; TECHNICAL PRESENTATIONS;

EID: 51749125239     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541995     Document Type: Conference Paper
Times cited : (7)

References (8)
  • 1
    • 0029289215 scopus 로고
    • An all-digital phase-locked loop with 50-cycle lock time suitable for high performance microprocessors
    • Apr
    • J. Dunning, G. Garcia, J. Lundberg, and Ed Nuckolls, " An all-digital phase-locked loop with 50-cycle lock time suitable for high performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 412-422, Apr. 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , Issue.11 , pp. 412-422
    • Dunning, J.1    Garcia, G.2    Lundberg, J.3    Nuckolls, E.4
  • 2
    • 33746657329 scopus 로고    scopus 로고
    • A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications
    • June
    • P.-L. Chen, C.-C. Chung, J.-N. Yang and C.-Y. Lee, "A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1275-1285, June 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.6 , pp. 1275-1285
    • Chen, P.-L.1    Chung, C.-C.2    Yang, J.-N.3    Lee, C.-Y.4
  • 3
    • 0033169554 scopus 로고    scopus 로고
    • An all digital phase-locked loop (ADPLL) based clock recovery circuit
    • Aug
    • T. Y. Hsu, B. J. Shieh, and C. Y. Lee, "An all digital phase-locked loop (ADPLL) based clock recovery circuit," IEEE J. Solid-State Circuits, vol.34, no. 8, pp. 1063-1073, Aug. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , Issue.8 , pp. 1063-1073
    • Hsu, T.Y.1    Shieh, B.J.2    Lee, C.Y.3
  • 6
    • 0036858657 scopus 로고    scopus 로고
    • A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling
    • Nov
    • K. J. Nowka et al., "A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling," IEEE J. Solid-State Circuits, vol. 37, no.11, pp. 1441-1447, Nov. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.11 , pp. 1441-1447
    • Nowka, K.J.1
  • 7
    • 0037319509 scopus 로고    scopus 로고
    • An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time
    • Feb
    • T. Watanabe and S. Yamauchi, "An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time," IEEE J. Solid-State Circuits, Vol. 38, no. 2, pp. 198-204, Feb. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.2 , pp. 198-204
    • Watanabe, T.1    Yamauchi, S.2
  • 8
    • 34547247708 scopus 로고    scopus 로고
    • A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
    • May
    • C.-T. Wu, W. Wang, I.-C. Wey and A.-Y Wu, "A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time," in Proc. IEEE Int. Symp. Circuits and Systems, pp. 4082-4085, May 2006.
    • (2006) Proc. IEEE Int. Symp. Circuits and Systems , pp. 4082-4085
    • Wu, C.-T.1    Wang, W.2    Wey, I.-C.3    Wu, A.-Y.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.