Reducing reversible circuit cost by adding lines

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2010, Pages 217-222

  Miller, D Michael ^a   Wille, Robert ^b   Drechsler, Rolf ^b  

^a UNIVERSITY OF VICTORIA   (Canada)

^b UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED SYNTHESIS; CIRCUIT OPTIMIZATION; QUANTUM COSTS; REVERSIBLE CIRCUITS; TRANSISTOR COUNT;

MANY VALUED LOGICS;

COST REDUCTION;

EID: 77955314326     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISMVL.2010.48     Document Type: Conference Paper

References (26)

1. V. V. Zhirnov, R. K. Cavin, J. A. Hutchby, and G. I. Bourianoff, "Limits to binary logic switch scaling - a gedanken model," Proc. of the IEEE, vol. 91, no. 11, pp. 1934-1939, 2003.
2. R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Dev., vol. 5, p. 183, 1961.
3. C. H. Bennett, "Logical reversibility of computation," IBM J. Res. Dev, vol. 17, no. 6, pp. 525-532, 1973.
4. B. Desoete and A. de Vos, "A reversible carry-look-ahead adder using control gates," INTEGRATION, the VLSI Journal, vol. 33, no. 1-2, pp. 89-104, 2002.
5. T. Simonite, "Error-check breakthrough in quantum computing," New Scientist, June 8 2006.
6. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, "Reversible logic circuit synthesis," in Proc. Int'l Conf. on CAD, 2002, pp. 125-132.
7. A. Agrawal and N. Jha, "Reversible logic synthesis," in Proc. Design, Automation and Test in Europe, 2004, pp. 1384-1385.
8. J. Donald and N. K. Jha, "Reversible logic synthesis with Fredkin and Peres gates," J. Emergin Technology Computing Systems, vol. 4, no. 1, pp. 1-19, 2008.
9. P. Gupta, A. Agrawal, and N. K. Jha, "An algorithm for synthesis of reversible logic circuits," IEEE Trans. on CAD, vol. 25, no. 11, pp. 2317-2330, Nov. 2006.
10. D. M. Miller, D. Maslov, and G. W. Dueck, "A transformation based algorithm for reversible logic synthesis," in Proc. Design Automation Conf., 2003, pp. 318-323.
11. D. Maslov, G. W. Dueck, and D. M. Miller, "Techniques for the synthesis of reversible Toffoli networks," ACM Trans. Des. Autom. Electron. Syst., vol. 12, no. 4, pp. 42.1-42.28, 2007.
12. M. Saeedi, M. Sedighi, and M. S. Zamani, "A novel synthesis algorithm for reversible circuits," in Proc. Int'l Conf. on CAD, 2007, pp. 65-68.
13. M. Saeedi, M. S. Zamani, and M. Sedighi, "On the behavior of substitution-based reversible circuit synthesis algorithms: Investigation and improvement," in Proc. IEEE Computer Society Symp. on VLSI, 2007, pp. 428-436.
14. K. Fazel, M. Thornton, and J. E. Rice, "ESOP-based Toffoli gate cascade generation," in Proceedings IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), 2007, pp. 206-209.
15. R. Wille, D. Große, G. Dueck, and R. Drechsler, "Reversible Logic Synthesis with Output Permutation," in VLSI Design, 2009, pp. 189-194.
16. K. Iwama, Y. Kambayashi, and S. Yamashita, "Transformation rules for designing CNOT-based quantum circuits," in Proc. Design Automation Conf., 2002, pp. 419-424.
17. D. Maslov, C. Young, D. M. Miller, and G. W. Dueck, "Quantum circuit simplification using templates," in Proc. Design, Automation and Test in Europe, 2005, pp. 1208-1213. (Pubitemid 44172174)
18. J. Zhong and J.C. Muzio, "Using crosspoint faults in simplifying Toffoli networks," in International IEEE Northeast Workshop on Circuits and Systems, 2006, pp. 129-132.
19. A. Barenco, C. Bennett, R. Cleve, D. DiVinchenzo, N. Margolus, P. Shor, T. Sleator, J. Smolin, and H. Weinfurter, "Elementary gates for quantum computation," Physical Review A, vol. 52, pp. 3457-3467, 1995.
20. R. Wille and R. Drechsler, "BDD-based Synthesis of Reversible Logic for Large Functions," in Proc. Design Automation Conf., 2009, pp. 270-275.
21. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, "Synthesis of reversible logic circuits," IEEE Trans. on CAD, vol. 22, no. 6, pp. 710-722, 2003.
22. M. Nielsen and I. Chuang, Quantum Computation and Quantum Information. Cambridge Univ. Press, 2000.
23. R. Wille, D. Große, L. Teuber, G. W. Dueck, and R. Drechsler, "RevLib: An online resource for reversible functions and reversible circuits," in Int'l Symp. on Multi-Valued Logic, 2008, pp. 220-225, RevLib is available at www.revlib.org.
24. M. K. Thomson and R. Glück, "Optimized reversible binary-coded decimal adders," J. of Systems Architecture, vol. 54, pp. 697-706, 2008.
25. D. Maslov and G. W. Dueck, "Reversible cascades with minimal garbage," IEEE Trans. on CAD, vol. 23, no. 11, pp. 1497-1509, 2004.
26. R. Wille, D. Große, D. M. Miller, and R. Drechsler, "Equivalence checking of reversible circuits," in Proc. Int'l Symp. on Multiple-valued Logic, 2009.