Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 966-978

  Wilhelm, Reinhard ^a,b   Grund, Daniel ^a   Reineke, Jan ^a   Schlickling, Marc ^a,c   Pister, Markus ^a,c   Ferdinand, Christian ^c  

^a SAARLAND UNIVERSITY   (Germany)

^b Leibniz Center for Computer Science   (Germany)

^c AbsInt GmbH   (Germany)

Author keywords

Memory hierarchy; Pipelines; Processor architecture; Timing predictability

Indexed keywords

AERONAUTICS INDUSTRY; ANALYSIS METHOD; ANALYSIS TOOLS; ARCHITECTURAL FEATURES; EMBEDDED DOMAINS; EMBEDDED HARD REAL-TIME SYSTEM; MEASUREMENT-BASED; MEMORY HIERARCHY; MULTICORE ARCHITECTURES; PROCESSOR ARCHITECTURES; STATIC TIMING ANALYSIS; TIMING CONSTRAINTS;

ARCHITECTURE; EMBEDDED SYSTEMS; INDUSTRY; NANOTECHNOLOGY; PIPELINES; PROFITABILITY; REAL TIME SYSTEMS; SOFTWARE ARCHITECTURE; TIME MEASUREMENT; TIMING CIRCUITS;

PIPELINE PROCESSING SYSTEMS;

EID: 77955209042     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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