-
3
-
-
84872094294
-
An optimal memory allocation scheme for scratch-pad-based embedded systems
-
November
-
O. Avissar, R. Barua, and D. Stewart. An Optimal Memory Allocation Scheme for Scratch-Pad-Based Embedded Systems. ACM Transactions on Embedded Computing Systems, 1(1):6-26, November 2002.
-
(2002)
ACM Transactions on Embedded Computing Systems
, vol.1
, Issue.1
, pp. 6-26
-
-
Avissar, O.1
Barua, R.2
Stewart, D.3
-
4
-
-
0036045884
-
Scratchpad memory: A design alternative for cache on-chip memory in embedded systems
-
May
-
R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel. Scratchpad Memory: A Design Alternative for Cache On-chip Memory in Embedded Systems. In 10th Int. Symp. on Hardware/Software Codesign (CODES), May 2002.
-
(2002)
10th Int. Symp. on Hardware/Software Codesign (CODES)
-
-
Banakar, R.1
Steinke, S.2
Lee, B.-S.3
Balakrishnan, M.4
Marwedel, P.5
-
5
-
-
2342485411
-
A Timing Analysis Language - (TAL) - Programmer's manual
-
Dept. of Computer Sciences, University of Texas, Ausin, Tx, Usa
-
M. Chen. A Timing Analysis Language - (TAL) - Programmer's Manual. Technical report, Dept. of Computer Sciences, University of Texas, Ausin, TX, USA, 1987.
-
(1987)
Technical Report
-
-
Chen, M.1
-
8
-
-
0013401912
-
Embedded systems roadmap
-
L. Eggermont. Embedded Systems Roadmap. Technical report, STW, http://www.stw.nl/progress/ESroadmap/index.html, 2002.
-
(2002)
Technical Report
-
-
Eggermont, L.1
-
9
-
-
85008006728
-
Exploiting fixed programs in embedded systems: A loop cache example
-
January
-
S.C.A. Gordon-Ross and F. Vahid. Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example. Computer Architecture Letters, January 2002.
-
(2002)
Computer Architecture Letters
-
-
Gordon-Ross, S.C.A.1
Vahid, F.2
-
10
-
-
0029514487
-
Worst case timing analysis of RISC processors: R3000/R3010
-
Y. Hur, Y.H. Bea, S. Kin, B. Rhee, W.L. Min, C.Y. Park, M. Lee, H. Shin, and C.S. Kim. Worst Case Timing Analysis of RISC Processors: R3000/R3010. In Proceedings of the 16th Real-Time Systems Symposium, pages 308-319, 1995.
-
(1995)
Proceedings of the 16th Real-time Systems Symposium
, pp. 308-319
-
-
Hur, Y.1
Bea, Y.H.2
Kin, S.3
Rhee, B.4
Min, W.L.5
Park, C.Y.6
Lee, M.7
Shin, H.8
Kim, C.S.9
-
11
-
-
2442616134
-
-
ILOG. CPLEX. http://www.ilog.com/products/cplex.
-
CPLEX
-
-
-
13
-
-
2442465957
-
Consideration of optimizing compilers in the context of WCET analysis
-
GI Gesellschaft für Informatik e.V., Oct.
-
R. Kirner and P. Puschner. Consideration of Optimizing Compilers in the Context of WCET Analysis. In Proc. Deutsche Informatiktage 2000, Bad Schussenried, pages 123-126. GI Gesllschaft für Informatik e.V., Oct. 2000.
-
(2000)
Proc. Deutsche Informatiktage 2000, Bad Schussenried
, pp. 123-126
-
-
Kirner, R.1
Puschner, P.2
-
14
-
-
2442502645
-
International workshop on WCET analysis - Summary
-
Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 1-3/182-1, 1040 Vienna, Austria
-
R. Kirner and P. Puschner. International Workshop on WCET Analysis - Summary. Research Report 12/2002, Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 1-3/182-1, 1040 Vienna, Austria, 2002.
-
(2002)
Research Report
, vol.12
, Issue.2002
-
-
Kirner, R.1
Puschner, P.2
-
16
-
-
0033359006
-
Instruction fetch energy reduction using loop caches for embedded applications with small tight loops
-
San Diego, CA, USA, August
-
L. H. Lee, B. Moyer, and J. Arends. Instruction Fetch Energy Reduction Using Loop Caches For Embedded Applications with small Tight Loops. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), San Diego, CA, USA, August 1999.
-
(1999)
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED)
-
-
Lee, L.H.1
Moyer, B.2
Arends, J.3
-
20
-
-
0003039244
-
An accurate worst case timing analysis for RISC processors
-
S. Lim, Y.H. Bea, G.T. Jang, B. Rhee, S.L. Min, C.Y. Park, H. Shin, and C.S. Kim. An Accurate Worst Case Timing Analysis for RISC Processors. In Proceedings of the 15th Real-Time Systems Symposium, pages 97-108, 1994.
-
(1994)
Proceedings of the 15th Real-time Systems Symposium
, pp. 97-108
-
-
Lim, S.1
Bea, Y.H.2
Jang, G.T.3
Rhee, B.4
Min, S.L.5
Park, C.Y.6
Shin, H.7
Kim, C.S.8
-
21
-
-
2442448452
-
Approaches to addressing the memory wall
-
November, Univ. Brisbane
-
P. Machanik. Approaches to Addressing the Memory Wall. Technical Report, November, Univ. Brisbane, 2002.
-
(2002)
Technical Report
-
-
Machanik, P.1
-
22
-
-
0002506443
-
Evaluating tight execution time bounds of programs by annotations
-
A.K. Mok, P. Amerasinghe, M. Chen, and K. Tantisirivat. Evaluating Tight Execution Time Bounds of Programs by Annotations. In Proc. of the 6th IEEE Workshop on Real-Time Operating Systems and Software, pages 74-80, 1989.
-
(1989)
Proc. of the 6th IEEE Workshop on Real-time Operating Systems and Software
, pp. 74-80
-
-
Mok, A.K.1
Amerasinghe, P.2
Chen, M.3
Tantisirivat, K.4
-
25
-
-
0013225410
-
A review of worst-case execution-time analysis (Editorial)
-
P. Puschner and A. Burns. A review of Worst-Case Execution-Time Analysis (Editorial). Journal of Real-Time Systems, 18:115-128, 1999.
-
(1999)
Journal of Real-time Systems
, vol.18
, pp. 115-128
-
-
Puschner, P.1
Burns, A.2
-
26
-
-
0004112038
-
-
Addison Wesley, Massachusetts
-
R. Sedgewick. Algorithms. Addison Wesley, Massachusetts, 1988.
-
(1988)
Algorithms
-
-
Sedgewick, R.1
-
27
-
-
2442506886
-
-
PhD thesis, (in German), Embedded Systems Group, CS Dept., University of Dortmund, Dortmund, Germany
-
S. Steinke. Investigation of the Potential for Energy Savings in Embedded Systems enabled by Energy Optimizing Compilers. PhD thesis, (in German), Embedded Systems Group, CS Dept., University of Dortmund, Dortmund, Germany, 2003.
-
(2003)
Investigation of the Potential for Energy Savings in Embedded Systems Enabled by Energy Optimizing Compilers
-
-
Steinke, S.1
-
28
-
-
0036953785
-
Reducing energy consumption by dynamic copying of instructions onto onchip memory
-
S. Steinke, N. Grunwald, L. Wehmeyer, R. Banakar, M. Balakrishnan, and P. Marwedel. Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. Int. Symp. on System Synthesis (ISSS), pages 213-218, 2002.
-
(2002)
Int. Symp. on System Synthesis (ISSS)
, pp. 213-218
-
-
Steinke, S.1
Grunwald, N.2
Wehmeyer, L.3
Banakar, R.4
Balakrishnan, M.5
Marwedel, P.6
-
29
-
-
84893786147
-
Assigning program and data objects to scratchpad for energy reduction
-
S. Steinke, L.Wehmeyer, B.-S. Lee, and P. Marwedel. Assigning Program and Data Objects to Scratchpad for Energy Reduction. Design, Automation and Test in Europe (DATE), pages 409-417, 2002.
-
(2002)
Design, Automation and Test in Europe (DATE)
, pp. 409-417
-
-
Steinke, S.1
Wehmeyer, L.2
Lee, B.-S.3
Marwedel, P.4
-
30
-
-
2442552998
-
-
Master's thesis, (in German), Embedded Systems Group, CS Dept., University of Dortmund, Dortmund, Germany
-
M. Theokharidis. Energiemessung von ARM7TDMI Prozessor-Instruktionen. Master's thesis, (in German), Embedded Systems Group, CS Dept., University of Dortmund, Dortmund, Germany, 2000.
-
(2000)
Energiemessung von ARM7TDMI Prozessor-Instruktionen
-
-
Theokharidis, M.1
-
33
-
-
84957036203
-
A framework for loop distribution on limited on-chip memory processors
-
L. Wang, W. Tembe, and S. Pande. A Framework for Loop distribution on Limited On-Chip Memory Processors. In Proceedings of the 9th International Conference on Compiler Construction, CC/ETAPS'00, volume 1781 of LNCS, pages 141-156, 2000.
-
(2000)
Proceedings of the 9th International Conference on Compiler Construction, CC/ETAPS'00, Volume 1781 of LNCS
, vol.1781
, pp. 141-156
-
-
Wang, L.1
Tembe, W.2
Pande, S.3
-
34
-
-
0030149507
-
CACTI: An enhanced access and cycle time model
-
S. Wilton and N. Jouppi. CACTI: An enhanced access and cycle time model. Int. Journal on Solid State Circuits, 31(5):677-688, 1996.
-
(1996)
Int. Journal on Solid State Circuits
, vol.31
, Issue.5
, pp. 677-688
-
-
Wilton, S.1
Jouppi, N.2
-
37
-
-
0027684495
-
Pipelined processors and worst case execution times
-
N. Zhand, N.A. Burns, and M. Nicholson. Pipelined Processors and Worst Case Execution Times. Real-Time Systems, 4(5):319-343, 1993.
-
(1993)
Real-time Systems
, vol.4
, Issue.5
, pp. 319-343
-
-
Zhand, N.1
Burns, N.A.2
Nicholson, M.3
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