The influence of processor architecture on the design and the results of WCET tools

Proceedings of the IEEE

Volumn 91, Issue 7, 2003, Pages 1038-1054

  Heckmann, Reinhold ^a   Langenbach, Marc ^b   Thesing, Stephan ^b   Wilhelm, Reinhard ^b  

^a AbsInt Angewandte Informatik GmbH   (Germany)

^b SAARLAND UNIVERSITY   (Germany)

Author keywords

Predictability, processor model; Real time, static analysis; Worst case execution time

Indexed keywords

BUFFER STORAGE; DIGITAL SIGNAL PROCESSING; OPTIMIZATION; PREDICTIVE CONTROL SYSTEMS; REAL TIME SYSTEMS;

PREDICTABILITY; PROCESSOR MODEL; STATIC ANALYSIS; WORST CASE EXECUTION TIMES (WCET);

PROGRAM PROCESSORS;

EID: 6944231166     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.814618     Document Type: Conference Paper

References (20)

1. P. Cousot and R. Cousot, "Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoinls," presented at the Proc. 4th ACM Symp. Principles of Programming Languages, 1977.
2. F. Nielson, H. R. Nielson, and C. Hankin, Principles of Program Analysis. Berlin, Germany: Springer-Verlag, 1999.
3. H. Theiling, "Extracting safe and precise control flow from binaries," presented at the Proc. 7th Int. Conf. Real-Time Computing Systems and Applications (RTCSA), Cheju Island, South Korea, 2000.
4. C. A. Healy, R. D. Arnold, F. Mueller, D. B. Whalley, and M. G. Harmon, "Bounding pipeline and instruction cache performance," IEEE Trans. Comput., vol. 48, pp. 53-70, Jan. 1999.
5. C. A. Healy, D. B. Whalley, and M. G. Harmon, "Integrating the timing analysis of pipelining and instruction caching," Proc: IEEE Real-Time Systems Symp., pp. 288-297, Dec. 1995.
6. Y.-T. S. Li, S. Malik, and A. Wolfe, "Cache modeling for real-time software: Beyond direct mapped instruction caches," presented at the IEEE Real-Time Systems Symp., Jan. 1997.
7. T. Lundqvist and P. Stenström, "Integrating path and timing analysis using instruction-level simulation techniques," in Proc. ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, F. Mueller and A. Bestavros, Eds., 1998, vol. 1474, Lecture Notes in Computer Science, pp. 1-15.
8. _, "An integrated path and timing analysis method based on cycle-level symbolic execution," Real-Time Systems, vol. 17, pp. 183-207, Nov. 1999.
9. J. Engblom, "Processor pipelines and static worst-case execution time analysis," Ph.D. dissertation, Uppsala Univ., 2002.
10. A. Colin and I. Puaut, "A modular and retargetable framework for tree-based WCET analysis," in 13th Euromicro Conf. Real-Time Systems. June 2001, pp. 37-44,
11. A. Smith, "Cache memories," ACM Comput. Surv., vol. 14, no. 3, 1983.
12. C. Ferdinand, "Cache behavior prediction for real-time systems," Ph.D. dissertation, Univ. Saarlandes, Saarbruecken, Germany, 1997.
13. C. Ferdinand, F. Martin, and R. Wilhelm, "Applying compiler techniques to cache behavior prediction," presented at the Proc. ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, 1997.
14. C. Ferdinand, F. Martin, R. Wilhelm, and M. Alt, "Cache behavior prediction by abstract interpretation," in Science of Computer Programming. Amsterdam, The Netherlands: Elsevier, 1998.
15. MPC750 RISC Microprocessor User's Manual, 1997.
16. M. Alt, C. Ferdinand, F. Martin, and R. Wilhelm, "Cache behavior prediction by abstract interpretation," in Proc. SAS'96, Static Analysis Symp. Berlin, Germany; Springer-Verlag, 1996, vol. 1145, Lecture Notes in Computer Science.
17. R. Wilhelm and D. Maurer, Compiler Design. Reading, MA: Addison-Wesley, 1995, International Computer Science Series. 2nd printing.
18. J. Schneider, "Statische pipeline - Analyze für echtzeitsysteme," Dipl. thesis, Univ. Saarland, Saarbruecken, Germany, 1998.
19. J. Schneider and C. Ferdinand, "Pipeline behavior prediction for superscalar processors by abstract interpretation," presented at the Proc. ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, 1999.
20. S. Thesing, J. Souyris, R. Heckmann, F. Randimbivololona, M. Langenbach, R. Wilhelm, and C. Ferdinand, "An abstract interpretation-based timing validation of hard real-time avionics software," Proc. Performance and Dependability Symp., to be published.