A case for FAME: FPGA architecture model execution

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 290-301

  Tan, Zhangxi ^a   Waterman, Andrew ^a   Cook, Henry ^a   Bird, Sarah ^a   Asanović, Krste ^a   Patterson, David ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE RESEARCH; COST PERFORMANCE; DATA SET SIZE; FPGA ARCHITECTURES; HARDWARE MECHANISM; HARDWARE PARTITIONING; MULTI CORE; MULTI-LEVEL MEMORY HIERARCHY; OPERATING SYSTEMS; ORDERS OF MAGNITUDE; PARALLEL BENCHMARKS; SIMULATION METHODOLOGY; SIMULATION SPEED-UP; SOFTWARE ARCHITECTURE MODEL; TARGET ARCHITECTURES; TARGET MACHINES; TIME-SCALES; TIMING MODELS;

COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; EXPERIMENTS; SIMULATORS;

SOFTWARE ARCHITECTURE;

EID: 77954982097     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1815999     Document Type: Conference Paper

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