A multithreaded soft processor for SoPC area reduction

Proceedings - 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006

Volumn , Issue , 2006, Pages 131-140

  Fort, Blair ^a   Capalija, Davor ^a   Vranesic, Zvonko G ^a   Brown, Stephen D ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTELLECTUAL PROPERTY; LOGIC DESIGN; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS;

CONTROLLING SYSTEMS; MULTITHREADING CAPABILITIES; PROCESSORS CONTROL IP BLOCKS; SINGLE-THREADED PROCESSORS;

PROGRAM PROCESSORS;

EID: 34547419763     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2006.10     Document Type: Conference Paper

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