ATLAS: A chip-multiprocessor with transactional memory support

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 3-8

  Njoroge, Njuguna ^a   Casper, Jared ^a   Wee, Sewook ^a   Teslyar, Yuriy ^a   Ge, Daxia ^a   Kozyrakis, Christos ^a   Olukotun, Kunle ^a  

^a Stanford University

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE; CONCURRENCY CONTROL; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PERSONAL COMPUTERS;

COARSE-GRAIN PARALLEL TASKS; CONCURRENCY MANAGEMENT; TRANSACTIONAL MEMORY (TM);

INTERCONNECTION NETWORKS;

EID: 34548297530     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364558     Document Type: Conference Paper

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